IP Library Granted Patent US 9,305,911
Granted Patent B2
US 9,305,911 · App. 14/097,459 · Granted Apr 5, 2016

Devices and stacked microelectronic packages with package surface conductors and adjacent trenches and methods of their fabrication

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Quick Facts
Patent No.
US 9,305,911
App. No.
14/097,459
Granted
Apr 5, 2016
Kind
B2
Abstract

Embodiments of methods for forming microelectronic device packages include forming a trench on a surface of a package body in an area adjacent to where first and second package surface conductors will be (or have been) formed on both sides of the trench. The method also includes forming the first and second package surface conductors to electrically couple exposed ends of various combinations of device-to-edge conductors. The trench may be formed using laser cutting, drilling, sawing, etching, or another suitable technique. The package surface conductors may be formed by dispensing (e.g., coating, spraying, inkjet printing, aerosol jet printing, stencil printing, or needle dispensing) one or more conductive materials on the package body surface between the exposed ends of the device-to-edge conductors.

Claims (33)

1. A method comprising:

forming a trench in a sidewall of a package body, wherein first, second, third, and fourth exposed ends of first, second, third, and fourth device-to-edge conductors are exposed at the sidewall of the package body;

forming a first package conductor over the sidewall along a first side of the trench to electrically couple the first exposed end of the first device-to-edge conductor and the second exposed end of the second device-to-edge conductor; and

forming a second package surface conductor over the sidewall along an opposite second side of the trench to electrically couple the third exposed end of the third device-to-edge conductor and the fourth exposed end of the fourth device-to-edge conductor, wherein the first and second package surface conductors are not electrically shorted across the trench.

2. The method of claim 1 , wherein forming the trench comprises using a trench formation method selected from laser cutting, drilling, and sawing.

3. The method of claim 1 , wherein forming the trench comprises forming a trench with a substantially rectangular cross-sectional shape.

4. The method of claim 1 , wherein forming the trench comprises forming a trench that is substantially perpendicular to the sidewall of the package body.

5. The method of claim 1 , wherein forming the trench comprises forming a trench that is not perpendicular to the sidewall of the package body.

6. The method of claim 1 , wherein forming the trench comprises forming a trench with a substantially circular cross-sectional shape.

7. The method of claim 1 , wherein forming the trench is performed before forming the first and second package surface conductors.

8. The method of claim 1 , wherein forming the trench is performed after forming the first and second package surface conductors.

9. The method of claim 1 , wherein forming the first and second package surface conductors comprises dispensing one or more conductive materials on the sidewall using one or more dispensing methods selected from coating, spraying, dispensing, evaporating, sputtering, inkjet printing, aerosol jet printing, stencil printing, and needle dispense.

10. The method of claim 1 , wherein forming the first and second package surface conductors comprises:

forming a conductive material layer over the sidewall, wherein the conductive material layer has a thickness that is less than a depth of the trench.

11. The method of claim 1 , wherein the first and second package surface conductors are formed from one or more conductive materials that are selected from an electrically conductive adhesive, conductive polymer, a polymer filled with conductive particles, a metal alloy, metal coated organic particles, metal coated ceramic particles, solder paste, solder-filled adhesive, nanoparticle-filled ink, a liquid metal, a metal-containing adhesive, a metal-containing epoxies, electrically-conductive pastes, indium, and bismuth.

12. The method of claim 1 , further comprising:

forming one or more additional trenches in the sidewall of the package body; and

forming one or more additional package surface conductors along sides of the one or more additional trenches.

13. The method of claim 1 , further comprising:

forming the package body by stacking a first microelectronic package that has a first sidewall on a second microelectronic package that has a second sidewall, wherein the first sidewall forms a first portion of the sidewall of the package body, the second sidewall forms a second portion of the sidewall of the package body, the first microelectronic package includes an embedded first microelectronic device that is electrically coupled with one or more of the first, second, third and fourth device-to-edge conductors, and the second microelectronic package includes an embedded second microelectronic device that is electrically coupled with one or more other ones of the first, second, third and fourth device-to-edge conductors.

14. A device, comprising:

a package body having a package sidewall, a first device-to-edge conductor with a first exposed end at the package sidewall, a second device-to-edge conductor with a second exposed end at the package sidewall, a third device-to-edge conductor with a third exposed end at the package sidewall, and a fourth device-to-edge conductor with a fourth exposed end at the package sidewall;

a trench formed in the package sidewall;

a first package conductor formed over the package sidewall along a first side of the trench that electrically couples the first exposed end of the first device-to-edge conductor and the second exposed end of the second device-to-edge conductor; and

a second package surface conductor formed over the package sidewall along an opposite second side of the trench that electrically couples the third exposed end of the third device-to-edge conductor and the fourth exposed end of the fourth device-to-edge conductor, wherein the first and second package surface conductors are not electrically shorted across the trench.

15. The device of claim 14 , wherein the trench has a substantially rectangular cross-sectional shape.

16. The device of claim 14 , wherein the trench is substantially perpendicular to the package sidewall.

17. The device of claim 14 , wherein the trench is not perpendicular to the package sidewall.

18. The device of claim 14 , wherein the trench has a substantially circular cross-sectional shape.

19. The device of claim 14 , wherein the package body comprises:

a first microelectronic package that has an embedded first microelectronic device that is electrically coupled with one or more of the first, second, third and fourth device-to-edge conductors, and a first sidewall that forms a first portion of the package sidewall; and

a second microelectronic package stacked on the first microelectronic package, wherein the second microelectronic package has an embedded second microelectronic device that is electrically coupled with one or more other ones of the first, second, third and fourth device-to-edge conductors, and a second sidewall that forms a second portion of the package sidewall.

20. The device of claim 14 , wherein the package surface conductor is formed from one or more conductive materials selected from an electrically conductive adhesive, conductive polymer, a polymer filled with conductive particles, a metal alloy, metal coated organic particles, metal coated ceramic particles, solder paste, solder-filled adhesive, nanoparticle-filled ink, a liquid metal, a metal-containing adhesive, a metal-containing epoxies, electrically-conductive pastes, indium, and bismuth.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FILING AND REMOVE APPL. NO. 14085520 REPLACE IT WITH 14086520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Mar 1, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037926/0642 →
CORRECTIVE ASSIGNMENT OF INCORRECT PATENT APPLICATION NUMBER 14085520 ,PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0399. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037785/0454 →
CORRECTIVE ASSIGNMENT OF INCORRECT NUMBER 14085520 PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTON OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037785/0568 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037792/0227 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037879/0581 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 037458 FRAME 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Jan 14, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037515/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 037458 FRAME 0399. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Jan 14, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037515/0390 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FOUNDING, INC.
Reel/Frame 037458/0420 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FOUNDING, INC.
Reel/Frame 037458/0399 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0790 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032445/0493 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032445/0577 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., COLLATERAL AGENT
Reel/Frame 032445/0689 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 5, 2013
From: VINCENT, MICHAEL B.; WRIGHT, JASON R.; YAP, WENG F.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031721/0362 →