System and method for controlling bypass of a voltage regulator
View Patent ↗A voltage regulator bypass circuit to control bypass of a voltage regulator of an integrated circuit device, the voltage regulator bypass circuit including a first voltage detector, a second voltage detector, and circuit. The first voltage detector to detect that a core circuitry voltage level is above a first threshold and to assert a first detect signal at an output in response to the detection. The second voltage detector to detect that an unregulated supply voltage is above a second threshold and to assert a second detect signal at an output in response to the detection. The circuit having a first input coupled to the output of the first voltage detector and a second input coupled to the output of the second voltage detector, the circuit to bypass the voltage regulator in response the output of the latch being cleared.
1. A method for controlling a bypass of a voltage regulator of an integrated circuit (IC) device, the method comprising:
detecting a first condition comprising an assertion of a test mode signal at an external pin of the IC device;
detecting a second condition comprising a core circuitry supply voltage being above a first threshold;
detecting a third condition comprising the core circuitry supply voltage rising above the first threshold prior to an unregulated voltage supply rising above a second threshold; and
bypassing the voltage regulator to enter a test mode in response to the first condition, the second condition, and the third condition being met.
2. The method of claim 1 , wherein:
detecting the second condition further comprises asserting a first detect signal in response to detecting that the core circuitry voltage level is above the first threshold;
detecting the second condition further comprises asserting a second detect signal in response to detecting that the unregulated voltage is above the second threshold;
detecting the third condition comprises asserting a bypass mode signal responsive to the first detect signal being asserted before the second detect signal; and
bypassing the voltage regulator comprises bypassing the voltage regulator responsive to the assertion of the bypass mode signal.
3. The method of claim 2 , further comprising:
introducing a delay in a signal path of the first detect signal and the test mode signal;
setting a latch to clear in response both to the assertion of the test mode signal and to the first detect signal being asserted before the second detect signal; and
asserting the bypass mode signal comprises asserting the bypass mode signal in response to setting the latch to clear.
4. The method of claim 1 , wherein the third condition further comprises the unregulated supply voltage also being above a third threshold.
5. The method of claim 4 , wherein:
the first threshold represents a voltage level expected for core circuitry of the IC device during a power-on reset of the IC device;
the second threshold represents a voltage level expected for the unregulated supply voltage during a power-on reset of the IC device; and
the third threshold represents a minimum standby voltage expected to maintain the core circuitry in a standby state.
6. The method of claim 1 , wherein:
the first threshold represents a voltage level expected for core circuitry of the IC device during a power-on reset of the IC device; and
the second threshold represents a voltage level expected for the unregulated supply voltage during a power-on reset of the IC device.
7. The method of claim 1 , further comprising:
enabling the voltage regulator to enter a non-test mode in response to any of the first, second, or third conditions failing to be met.
8. The method of claim 7 , wherein:
bypassing the voltage regulator to enter the test mode comprises powering core circuitry of the IC device using an externally-supplied test voltage; and
enabling the voltage regulator to enter the non-test mode comprises powering the core circuitry using a regulated voltage output by the voltage regulator.
9. A method for controlling a bypass of a voltage regulator of an integrated circuit (IC) device, the method comprising:
detecting a first condition comprising an assertion of a test mode signal at an external pin of the IC device;
detecting a second condition comprising a core circuitry supply voltage rising above a first threshold prior to an unregulated voltage supply rising above a second threshold; and
bypassing the voltage regulator to enter a test mode in response to the first condition and the second condition being met.
10. The method of claim 9 , wherein:
detecting the second condition comprises asserting a first detect signal in response to detecting that the core circuitry voltage level is above the first threshold;
asserting a second detect signal in response to detecting that the unregulated voltage is above the second threshold;
detecting the second condition comprises asserting a bypass mode signal responsive to the first detect signal being asserted before the second detect signal; and
bypassing the voltage regulator comprises bypassing the voltage regulator responsive to the assertion of the bypass mode signal.
11. The method of claim 10 , further comprising:
introducing a delay in a signal path of the first detect signal and the test mode signal;
setting a latch to clear in response both to the assertion of the test mode signal and to the first detect signal being asserted before the second detect signal; and
asserting the bypass mode signal comprises asserting the bypass mode signal in response to setting the latch to clear.
12. The method of claim 9 , wherein the second condition further comprises the unregulated supply voltage also being above a third threshold.
13. The method of claim 12 , wherein:
the first threshold represents a voltage level expected for core circuitry of the IC device during a power-on reset of the IC device;
the second threshold represents a voltage level expected for the unregulated supply voltage during a power-on reset of the IC device; and
the third threshold represents a minimum standby voltage expected to maintain the core circuitry in a standby state.
14. The method of claim 9 , wherein:
the first threshold represents a voltage level expected for core circuitry of the IC device during a power-on reset of the IC device; and
the second threshold represents a voltage level expected for the unregulated supply voltage during a power-on reset of the IC device.
15. The method of claim 9 , further comprising:
enabling the voltage regulator to enter a non-test mode in response to either of the first or second conditions failing to be met.
16. The method of claim 15 , wherein:
bypassing the voltage regulator to enter the test mode comprises powering core circuitry of the IC device using an externally-supplied test voltage; and
enabling the voltage regulator to enter the non-test mode comprises powering the core circuitry using a regulated voltage output by the voltage regulator.
17. A method for controlling a bypass of a voltage regulator of an integrated circuit (IC) device, the method comprising:
detecting an assertion of a test mode signal at an external pin of the IC device;
asserting a bypass mode signal responsive to a core circuitry supply voltage rising above a first threshold prior to an unregulated voltage supply rising above a second threshold; and
bypassing the voltage regulator to enter a test mode of the IC device in response to the assertion of the test mode signal and the bypass mode signal, otherwise enabling the voltage regulator to enter a non-test mode in response to either of the test mode signal or the bypass mode signal failing to be asserted.
18. The method of claim 17 , wherein:
the first threshold represents a voltage level expected for core circuitry of the IC device during a power-on reset of the IC device; and
the second threshold represents a voltage level expected for the unregulated supply voltage during a power-on reset of the IC device.
19. The method of claim 17 , wherein:
bypassing the voltage regulator to enter the test mode comprises powering core circuitry of the IC device using an externally-supplied test voltage; and
enabling the voltage regulator to enter a non-test mode comprises powering the core circuitry using a regulated voltage output by the voltage regulator.
20. The method of claim 1 , further comprising:
detecting that the unregulated supply voltage also being above a third threshold, and wherein the third threshold represents a minimum standby voltage expected to maintain the core circuitry in a standby state.