Semiconductor devices with inner via
A semiconductor device includes a semiconductor substrate having an inactive area and a pair of active areas separated by the inactive area, a control terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area to define a conduction path during operation between a first conduction region in each active area and a second conduction region in each active area, a conduction terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area for electrical connection to each first conduction region, and a via extending through the semiconductor substrate, electrically connected to the conduction terminal, and positioned in the inactive area.
1. A semiconductor device comprising:
a semiconductor substrate comprising an inactive area and a pair of active areas separated by the inactive area;
a control terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area to define a conduction path during operation between a first conduction region in each active area and a second conduction region in each active area;
a conduction terminal supported by the semiconductor substrate and extending across the pair of active areas and the inactive area for electrical connection to each first conduction region; and
a via extending through the semiconductor substrate, electrically connected to the conduction terminal, and positioned in the inactive area.
2. The semiconductor device of claim 1 , wherein the control terminal is one of a plurality of gate fingers supported by the semiconductor substrate and extending across the pair of active areas and the inactive area.
3. The semiconductor device of claim 2 , wherein:
the conduction terminal is one of a plurality of source fingers supported by the semiconductor substrate, extending across the pair of active areas and the inactive area; and
the via is one of a plurality of source vias arranged in a single row in the inactive area, each source via being electrically connected to a respective one of the plurality of source fingers.
4. The semiconductor device of claim 2 , wherein the plurality of gate fingers are configured such that the semiconductor device has a uniform gate pitch.
5. The semiconductor device of claim 2 , wherein a pitch of the plurality of gate fingers varies between the pair of active areas and the inactive area.
6. The semiconductor device of claim 5 , wherein:
the conduction terminal is one of a plurality of source fingers supported by the semiconductor substrate, extending across the pair of active areas and the inactive area;
the via is one of a plurality of source vias, each source via being electrically connected to a respective one of the plurality of source fingers; and
each gate finger is bowed away from a respective source via of the plurality of source vias in the inactive area.
7. The semiconductor device of claim 1 , the via is elongated in a direction in which the conduction terminal extends across the pair of active areas and the inactive area.
8. The semiconductor device of claim 1 , further comprising a metal layer disposed on a back side of the semiconductor substrate opposite a front side of the semiconductor substrate on which the control terminal is supported, wherein:
the via is electrically connected to the metal layer; and
the metal layer is configured to be soldered to a ground plane of the semiconductor device.
9. The semiconductor device of claim 1 , wherein the via is centered along a lateral dimension of the conduction terminal, the lateral dimension corresponding with a direction in which the conduction terminal extends across the pair of active areas and the inactive area.
10. A transistor device comprising:
a semiconductor substrate comprising a pair of active areas and an inactive area disposed between the pair of active areas;
a plurality of control terminal fingers supported by the semiconductor substrate, each control terminal finger extending across the pair of active areas and the inactive area to define a conduction path during operation between a first conduction region in each active area and a second conduction region in each active area;
a plurality of conduction terminal fingers supported by the semiconductor substrate, each conduction terminal finger extending across the pair of active areas and the inactive area for electrical connection to a respective first conduction region in each active area; and
a plurality of vias extending through the semiconductor substrate, each via being positioned in the inactive area and electrically connected to a respective conduction terminal finger of the plurality of conduction terminal fingers.
11. The transistor device of claim 10 , wherein the plurality of control terminal fingers are configured such that the semiconductor device has a uniform control terminal pitch.
12. The transistor device of claim 10 , wherein a pitch of the plurality of control terminal fingers varies between the pair of active areas and the inactive area.
13. The transistor device of claim 10 , wherein each control terminal finger is bowed away from a respective via of the plurality of vias in the inactive area.
14. The transistor device of claim 10 , wherein each via of the plurality of vias is centered along a lateral dimension of a respective conduction terminal finger of the plurality of conduction terminal fingers, the lateral dimension corresponding with a direction in which the respective conduction terminal finger extends across the pair of active areas and the inactive area.
15. The transistor device of claim 10 , wherein:
each control terminal finger is configured as a gate terminal;
each conduction terminal finger is configured as a source finger;
each first conduction region is configured as a source region;
each second conduction region is configured as a drain region; and
the semiconductor substrate comprises a base substrate and a Group III-nitride semiconductor layer grown on the base substrate, the base substrate comprising silicon carbide.
16. A method of fabricating a semiconductor device, the method comprising:
forming an inactive area in a semiconductor substrate, the inactive area defining a pair of active areas separated by the inactive area;
forming a via through the semiconductor substrate in the inactive area;
forming a conduction terminal over the semiconductor substrate that extends across the pair of active areas and the inactive area, the conduction terminal being electrically connected to the via; and
forming a control terminal over the semiconductor substrate that extends across the pair of active areas and the inactive area to define a conduction region in each active area electrically connected to the conduction terminal.
17. The method of claim 16 , further comprising epitaxially growing a Group III-nitride semiconductor layer grown on a base substrate of the semiconductor substrate.
18. The method of claim 16 , wherein the semiconductor substrate comprises silicon carbide.
19. The method of claim 16 , wherein:
forming the control terminal comprises forming a plurality of gate fingers over the semiconductor substrate that extend across the pair of active areas and the inactive area; and
the plurality of gate fingers are configured such that the semiconductor device has a uniform gate pitch.
20. The method of claim 16 , wherein:
forming the control terminal comprises forming a plurality of gate fingers over the semiconductor substrate that extend across the pair of active areas and the inactive area; and
a pitch of the plurality of gate fingers varies between the pair of active areas and the inactive area.