Granted Patent B2

US 9,898,386 · App. 14/054,484 · Granted Feb 20, 2018

Abstract

Claims (72)

1. A method comprising:

retrieving, by at least one of one or more processors included in an endianness violation detection subsystem a load real data address corresponding to a load operation, and a store real data address corresponding to a store operation;

retrieving, by at least one of the one or more processors, a load size corresponding to the load operation and a store size corresponding to the store operation;

computing, by the one or more processors, a load real data address range based upon the load real data address and the load size and a store real data address range based upon the store real data address and the store size that overlaps the lead real data address range; wherein the store real data address range is included in store debug data generated by a first hardware unit in response to execution of the store operation, and wherein the load real data address range is included in load debug data generated by a second hardware unit in response to execution of the load operation;

determining, by at least one of the one or more processors, that at least one endianness relevant load attribute corresponding to the load operation is different than at least one endianness relevant store attribute corresponding to the store operation, the load size included in the one or more endianness relevant load attributes and the store size included in the one or more endianness relevant store attributes;

generating an endianness violation, by at least one of the one or more processors, in response to the determination;

filtering out, based on a first filter rule, future store debug data generated by the first hardware that corresponds to the store real data address range, wherein the future store debug data is located by one or more of the processors subsequent to the generation of the endianness violation; and

ignoring, by the one or more processors, the filtered out future store debug data.

2. The method of claim 1 further comprising:

determining that the load size is different than the store size; and

performing the generation of the endianness violation in response to the determination that the load size is different than the store size.

3. The method of claim 1 wherein, prior to the locating of the store real data address range that overlaps the load real data address range, the method further comprises:

obtaining, by at least one of the one or more processors, the future store debug data from the first hardware unit over one of a plurality of debug channels;

extracting, by at least one of the one or more processors, a store effective data address from the store debug data;

translating the store effective data address to a store real data address using a shadow memory management unit, wherein the shadow memory management unit receives memory management unit update information over one or more of the plurality of debug channels; and

storing the received store debug data and the store real data address in a lookup table entry.

4. The method of claim 1 wherein the first hardware unit executes the store operation and generates the store debug data, and wherein the second hardware unit executes the load operation and generates the load debug data.

5. The method of claim 4 further comprising:

retrieving, by at least one of the one or more processors, a first byte ordering type identifier corresponding to the first hardware unit, the first byte ordering type identifier included in the one or more endianness relevant store attributes;

retrieving a second byte ordering type identifier corresponding to the second hardware unit, the second byte ordering type identifier included in the one or more endianness relevant load attributes; and

generating the endianness violation in response to determining that the first byte ordering type identifier is different than the second byte ordering type identifier.

6. The method of claim 4 wherein the first hardware unit and the second hardware unit are different hardware unit types selected from the group consisting of a processor core and a hardware accelerator.

7. The method of claim 4 further comprising:

filtering, by at least one of the one or more processors, unfiltered debug data according to the first filter rule.

8. The method of claim 7 wherein, in response to generating the endianness violation, the method further comprises:

generating a second filter rule that filters out different debug data generated by the second hardware unit and corresponds to the load real data address range.

9. The method of claim 1 further comprising:

determining, by at least one of the one or more processors, a load effective instruction address of a load instruction and a store effective instruction address of a store instruction, the load instruction corresponding to the load operation and the store instruction corresponding to the store operation; and

including the load effective instruction address and the store effective instruction address in the endianness violation.

10. The method of claim 9 further comprising:

correlating, by a code correlation system, the load effective instruction address to a first source code address corresponding to the load instruction; and

correlating, by the code correlation system, the store effective instruction address to a second source code address corresponding to the store instruction.

11. A system comprising:

one or more hardware units;

one or more memories accessible by at least one of the one or more hardware units; and endianness analyzer circuitry configured to:

retrieve a load real data address corresponding to a load operation, and a store real data address corresponding to a store operation;

retrieve a load size corresponding to the load operation and a store size corresponding to the store operation;

compute a load real data address range based upon the load real data address and the lead size and a store real data address range based upon the store real data address that overlaps the load real data address range, wherein the store real data address range is included in store debug data generated by a first one of the one or more hardware units in response to execution of the store operation, and wherein the load real data address range is included in load debug data generated by a second one of the one or more hardware units in response to execution of the load operation;

determine that at least one endianness relevant load attribute corresponding to the load operation is different than at least one endianness relevant store attribute corresponding to the store operation, the lead size included in the one or mere endianness relevant lead attributes and the store size included in the one or more endianness relevant store attributes;

generate an endianness violation in response to the determination;

and determine a load effective instruction address of a load instruction and a store effective instruction address of a store instruction, the load instruction corresponding to the load operation and the store instruction corresponding to the store operation;

include the load effective instruction address and the store effective instruction address in the endianness violation;

correlate, by a code correlation system, the load effective instruction address to a first source code address corresponding to the load instruction;

correlate; by the code correlation system, the store effective instruction address to a second source code address corresponding to the store instruction;

filter out, based on a first filter rule, future store debug data generated by the one or more hardware units that corresponds to the store real data address range, wherein the future store debug data is located by the one or more hardware units subsequent to the generation of the endianness violation; and

ignore the filtered out future store debug data.

12. The system of claim 11 wherein the endianness analyzer circuitry is further configured to:

determine that the bad size is different than the store size; and

perform the generation of the endianness violation in response to the determination that the load size is different than the store size.

13. The system of claim 11 wherein the endianness analyzer circuitry is further configured to:

obtain the store debug data from the one or more hardware units over one of a plurality of debug channels prior to the locating of the store real data address range that overlaps the load real data address range;

extract a store effective data address from the future store debug data;

translate the store effective data address to a store real data address using a shadow memory management unit, wherein the shadow memory management unit receives memory management unit update information over one or more of the plurality of debug channels; and

store the received store debug data and the store real data address in a lookup table entry.

14. The system of claim 11 wherein the endianness analyzer circuitry is further configured to:

retrieve a first byte ordering type identifier corresponding to a first hardware unit that generates the store debug data, the first byte ordering type identifier included in the one or more endianness relevant store attributes;

retrieve a second byte ordering type identifier corresponding to a second hardware unit that generates the load debug data, the second byte ordering type identifier included in the one or more endianness relevant load attributes; and

generate the endianness violation in response to determining that the first byte ordering type identifier is different than the second byte ordering type identifier.

15. The system of claim 14 wherein the first hardware unit and the second hardware unit are different hardware unit types selected from the group consisting of a processor core and a hardware accelerator.

16. The system of claim 14 wherein the endianness analyzer circuitry is further configured to:

generate a second filter rule that filters out different debug data generated by the second hardware unit and corresponds to the load real data address range.

17. A device comprising:

a plurality of hardware units;

a shared memory area accessible by one or more of the plurality of hardware units; and

an endianness violation detection sub-system, communicatively coupled to the plurality of hardware units by corresponding debug channels and configured to:

retrieve a load real data address corresponding to a load operation, and a store real data address corresponding to a store operation;

retrieve a load size corresponding to the load operation and a store size corresponding to the store operation;

compute a load real data address range based upon the load real data address and the load size and a store real data address range based upon the store real data address that overlaps the load real data address range, wherein the store real data address range is included in store debug data generated by a first one of the plurality of hardware units in response to execution of the store operation, and wherein the load real data address range is included in load debug data generated by a second one of the plurality of hardware units in response to execution of the load operation;

determine that at least one endianness relevant load attribute corresponding to the load operation is different than at least one endianness relevant store attribute corresponding to the store operation, the load size included in the one or more endianness relevant load attributes and the store size included in the one or more endianness relevant store attributes;

generate are endianness violation, by at least one of the one or more processors, in response to the determination; and

filter out, based on a first filter rule, future store debug data generated by the one or more hardware units that corresponds to the store real data address range, wherein the future store debug data is located by one or more of the plurality of hardware units subsequent to the generation of the endianness violation; and

ignore the filtered out future store debug data.

Assignments (22)