Method of adding features to parameterized cells
View Patent ↗An electronic design automation (EDA) tool for adding a feature to a target parameterized cell (pcell) in an electronic circuit design includes a memory that stores the electronic circuit design, and a processor in communication with the memory. The processor defines a specification of an add-on pcell. The specification includes a feature to be added to the target pcell. The processor reads the properties associated with the target pcell and generates the add-on pcell based on its specification and the properties of the target pcell. The add-on pcell then is instantiated and bound to the target pcell, which adds the feature to the target pcell.
1. An electronic design automation (EDA) tool for adding a feature to a target parameterized cell (pcell) of a plurality of pcells of an electronic circuit design, the EDA tool comprising:
a memory that stores the electronic circuit design; and
a processor in communication with the memory, wherein the processor includes:
means for defining a specification of an add-on pcell, wherein the specification includes the feature to be added to the target pcell;
means for reading at least one property associated with the target pcell;
means for generating the add-on pcell based on the specification and the at least one property of the target pcell;
means for instantiating the add-on pcell; and
means for binding the add-on pcell to the target pcell, whereby the feature is added to the target pcell by way of the add-on pcell.
2. The EDA tool of claim 1 , wherein the at least one property of the target pcell includes at least one of coordinates of the target pcell with respect to the electronic circuit design, an orientation of the target pcell on the electronic circuit design, and at least one parameter associated with the target pcell.
3. The EDA tool of claim 2 , wherein the at least one parameter associated with the target pcell includes at least one of a length of the target pcell, a width of the target pcell, and a number of fingers of the target pcell.
4. The EDA tool of claim 1 , wherein the processor further includes means for updating the specification of the add-on pcell based on updates to the at least one property of the target pcell.
5. The EDA tool of claim 1 , wherein the add-on pcell and the target pcell have the same hierarchy level.
6. The EDA tool of claim 5 , wherein the means for binding binds the add-on pcell to the target pcell at a hierarchy level that is above hierarchy levels of the add-on and target pcells.
7. The EDA tool of claim 1 , wherein the feature is independent of one or more component description format (CDF) parameters associated with the target pcell.
8. The EDA tool of claim 1 , wherein the feature includes at least one of connectivity, stretch handles, abutment, pcell tiling, guard rings, taps for substrate connectivity, metal via stacks, and additional layers.
9. A method for adding a feature to a target parameterized cell (pcell) of a plurality of pcells of an electronic circuit design using an electronic design automation (EDA) tool, wherein the EDA tool includes a memory that stores the electronic circuit design and a processor in communication with the memory, the method comprising:
defining a specification of an add-on pcell with the processor, wherein the specification includes the feature to be added to the target pcell;
reading from the memory at least one property associated with the target pcell;
generating, by the processor, the add-on pcell based on the defined specification and the at least one property of the target pcell;
instantiating, by the processor, the add-on pcell;
binding, by the processor, the add-on pcell to the target pcell, whereby the feature is added to the target pcell by way of the add-on pcell; and
updating the electronic circuit design and storing the updated design in the memory.
10. The method of claim 9 , wherein the at least one property of the target pcell includes at least one of coordinates of the target pcell with respect to the electronic circuit design, an orientation of the target pcell on the electronic circuit design, and at least one parameter associated with the target pcell.
11. The method of claim 10 , wherein the at least one parameter associated with the target pcell includes at least one of a length of the target pcell, a width of the target pcell, and a number of fingers of the target pcell.
12. The method of claim 9 , further comprising updating the specification of the add-on pcell based on updates to the at least one property of the target pcell.
13. The method of claim 9 , wherein the add-on pcell and the target pcell have the same hierarchy level.
14. The method of claim 9 , further comprising binding the add-on pcell to the target pcell at a hierarchy level that is above hierarchy levels of the add-on and target pcells.
15. The method of claim 9 , wherein the feature is independent of or more component description format (CDF) parameters associated with the target pcell.
16. The method of claim 9 , wherein the feature includes at least one of connectivity, stretch handles, abutment, pcell tiling, guard rings, taps for substrate connectivity, metal via stacks, and additional layers.
17. An electronic design automation (EDA) tool for adding a feature to a target parameterized cell (pcell) of a plurality of pcells of an electronic circuit design, the EDA tool comprising:
a memory that stores the electronic circuit design; and
a processor in communication with the memory, wherein the processor includes:
means for defining a specification of an add-on pcell, wherein the specification includes the feature to be added to the target pcell;
means for reading at least one property associated with the target pcell;
means for generating the add-on pcell based on the specification and the at least one property of the target pcell;
means for instantiating the add-on pcell;
means for binding the add-on pcell to the target pcell, whereby the feature is added to the target pcell by way of the add-on pcell; and
means for updating the specification of the add-on pcell based on updates to the at least one property of the target pcell.