Granted Patent B2

US 8,782,478 · App. 14/048,362 · Granted Jul 15, 2014

Abstract

Claims (39)

1. A method for determining an imminent failure of a non-volatile memory array, the method comprising:

performing a first array integrity read operation of the non-volatile memory array until an error is detected;

determining that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage;

performing a second array integrity read operation of the non-volatile memory array, the second array integrity read operation comprising reading the array with a word line read voltage that is offset from the first threshold voltage and based on a predetermined width offset reference value;

performing a check sum on the non-volatile memory array subsequent to the second array integrity read operation to provide a check sum value; and

checking the check sum value to determine whether an imminent failure of the non-volatile memory is or is not indicated, wherein when the check sum value is equal to a predetermined check sum value an imminent failure in the non-volatile memory array is not indicated, and wherein when the check sum value is not equal to the predetermined check sum value an imminent failure in the non-volatile memory array is indicated.

2. The method of claim 1 , wherein the first array integrity read operation is accomplished by performing read operations of the non-volatile memory array while sweeping the word line read voltage within a predetermined range.

3. The method of claim 1 , wherein checking the check sum value further comprises the check sum value being a first value when all bits of the non-volatile memory array are programmed, and the check sum value being a second value when all bits of the non-volatile memory array are erased, wherein the first value is not equal to the second value and wherein the first value and the second value are different from any other checksum value associated with the memory array.

4. The method of claim 1 , wherein the predetermined width offset reference value is based on a predefined threshold voltage width including a margin.

5. The method of claim 1 , wherein the method is performed during a diagnostic mode of the non-volatile memory array.

6. The method of claim 1 , further comprising storing the first threshold voltage and the predetermined width offset reference value in predetermined locations of the non-volatile memory array.

7. A system, comprising:

a memory array having a plurality of memory cells, wherein each of the plurality of memory cells is coupled to a word line and a bit line;

a threshold voltage modulator coupled to the word line, wherein the threshold voltage modulator is configured to provide a range of voltage levels to the word line during a diagnostic mode of the system;

an error correction code (ECC) decoder coupled to the memory array; and

a memory controller coupled to the memory array, the threshold voltage modulator, and the ECC decoder, wherein the memory controller is configured to:

perform a first array integrity read operation of the memory array until an error is detected;

determine that the error is not ECC correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage;

perform a second array integrity read operation of the memory array, wherein the second array integrity read operation includes reading the array with a word line read voltage that is offset from the first threshold voltage and is based on a predetermined width offset reference value;

perform a check sum on the non-volatile memory array subsequent to the second array integrity read operation to provide a check sum value; and

check the check sum value to determine whether an imminent failure of the non-volatile memory is or is not indicated, wherein when the check sum value is equal to a predetermined check sum value an imminent failure in the non-volatile memory array is not indicated, and wherein when the check sum value is not equal to the predetermined check sum value an imminent failure in the non-volatile memory array is indicated.

8. The system of claim 7 , wherein the first array integrity read operation is accomplished by performing read operations of the memory array while sweeping the word line read voltage within a predetermined range.

9. The system of claim 7 , wherein the check sum value is a first value when all bits of the memory array are programmed and the check sum value is a second value when all bits of the memory array are erased, and wherein the first value is not equal to the second value and the first value and the second value are different from any other checksum value associated with the memory array.

10. The system of claim 7 , wherein the predetermined width offset reference value is based on a predefined threshold voltage width that includes a margin.

11. The system of claim 7 , wherein the memory controller is configured to check the check sum value during a diagnostic mode.

12. The system of claim 7 , wherein the first threshold voltage and the predetermined width offset reference value are stored in predetermined locations of the memory array.

13. A non-volatile memory system, comprising:

a non-volatile memory array having a plurality of memory cells, wherein each of the plurality of memory cells is coupled to a word line and a bit line;

a memory controller coupled to the memory array, wherein the memory controller is configured to:

perform a first array integrity read operation of the non-volatile memory array until an error is detected;

determine that the error is not error correction code (ECC) correctable, wherein a first word line voltage associated with the error is characterized as being a first threshold voltage;

perform a second array integrity read operation of the non-volatile memory array, wherein the second array integrity read operation includes reading the array with a word line read voltage that is offset from the first threshold voltage and is based on a predetermined width offset reference value;

perform a check sum on the non-volatile memory array subsequent to the second array integrity read operation to provide a check sum value; and

check the check sum value to determine whether an imminent failure of the non-volatile memory is or is not indicated, wherein when the check sum value is equal to a predetermined check sum value an imminent failure in the non-volatile memory array is not indicated, and wherein when the check sum value is not equal to the predetermined check sum value an imminent failure in the non-volatile memory array is indicated.

14. The system of claim 13 , wherein the first array integrity read operation is accomplished by performing read operations of the non-volatile memory array while sweeping the word line read voltage within a predetermined range.

15. The system of claim 13 , wherein the check sum value is a first value when all bits of the non-volatile memory array are programmed and the check sum value is a second value when all bits of the non-volatile memory array are erased, and wherein the first value is not equal to the second value and the first value and the second value are different from any other checksum value associated with the memory array.

16. The system of claim 13 , wherein the predetermined width offset reference value is based on a predefined threshold voltage width that includes a margin.

17. The system of claim 13 , wherein the memory controller is configured to check the check sum value during a diagnostic mode of the non-volatile memory array.

18. The system of claim 13 , wherein the first threshold voltage and the predetermined width offset reference value are stored in predetermined locations of the non-volatile memory array.

Assignments (20)