IP Library Patent Application 14104602
Patent Application
App. No. 14/104,602

CONFIGURABLE TEST EQUIPMENT

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Quick Facts
Patent No.
US None
App. No.
14/104,602
Abstract

An electronic component test device capable of testing electronic components in a plurality of test configurations. The device includes a probe head for providing a plurality of probe contact structures to an electronic component to be tested. The device includes an interconnect board coupled to the probe head. The interconnect board includes a plurality of conductive terminals, each of a first subset of the plurality of conductive terminals is coupled to one of a group of electrical signal lines for coupling to different types of external signals. The interconnect board includes a plurality of conductive lines. Each conductive line is coupled between a corresponding one of a plurality of conductive terminals in a second subset of the plurality of conductive terminals and a terminal for coupling to one of the plurality of probe contact structures. Each conductive terminal of the second subset is couplable by an interconnector of a plurality of interconnectors to a conductive terminal of multiple conductive terminals of the first subset based on a test configuration of the device.

Claims (43)

1 . An electronic component testing device capable of testing electronic components in a plurality of test configurations, comprising:

a probe head for providing a plurality of probe contact structures to an electronic component to be tested;

an interconnect board coupled to the probe head, the interconnect board including:

a plurality of conductive terminals, each of a first subset of the plurality of conductive terminals is coupled to one of a group of electrical signal lines for coupling to different types of external signals;

a plurality of conductive lines, each conductive line of the plurality is coupled between one of a plurality of conductive terminals in a second subset of the plurality of conductive terminals and a terminal for coupling to one of the plurality of probe contact structures; and

wherein each conductive terminal of the second subset is couplable by an interconnector of a plurality of interconnectors to a conductive terminal of multiple conductive terminals of the first subset based on a test configuration of the device.

2 . The device of claim 1 , wherein for at least some test configurations of the device, not all of the second subset of the plurality of conductive terminals are coupled to a conductive terminal of the first subset.

3 . The device of claim 1 , wherein the different types of external signals include at least one of a group consisting of: an analog ground signal, a digital ground signal, a power signal, an information signal.

4 . The device of claim 1 , further comprising a plurality of contact pads on the interconnect board coupled to the first subset of the plurality of conductive terminals for conveying the external signals.

5 . The device of claim 1 , further comprising:

a tester interface; and

a test head coupled to the tester interface, wherein the tester interface conveys the different types of external signals between the test head and the first subset of the plurality of conductive terminals on the interconnect board.

6 . The device of claim 1 , further comprising the plurality of probe contact structures.

7 . The device of claim 6 wherein the plurality of probe contact structures includes a plurality of probe pins that are selectively removable from the probe head depending upon the test configuration of the device.

8 . The device of claim 1 , wherein the plurality of interconnects include interconnects that are characterized as one type of a group consisting of: jumpers, switches, dip switches, resistors, wires, solid state relays, electromechanical relays, multiplexer, and receptacles.

9 . An electronic component test device comprising:

an interconnect board couplable between a probe head and a test head, the interconnect board includes:

a probe head area couplable to the probe head, the probe head area including a plurality of probe conductive terminals;

one or more conductive terminal areas, each conductive terminal area including:

a plurality of signal side conductive terminals, each of the plurality of signal side conductive terminals are couplable to convey a testing signal of a plurality of testing signals of the test head;

a plurality of probe side conductive terminals, each coupled to a respective probe conductive terminal of the plurality of probe conductive terminals;

a plurality interconnectors configurable to provide different combinations of connections between signal side conductive terminals of the plurality of signal side conductive terminals of a conductive terminal area and probe side conductive terminals of the plurality of probe side conductive terminals of the conductive terminal area for testing electronic components of different configurations.

10 . The device of claim 9 , further comprising the probe head, wherein the probe head comprises a plurality of probe pins couplable to the plurality of probe side conductive terminals.

11 . The device of claim 10 , wherein at least some of the probe pins of the plurality of probe pins are selectively removable from the probe head to accommodate for different electronic component configurations.

12 . The device of claim 10 wherein the probe head and the plurality of probe pins are designed to test die on a semiconductor wafer.

13 . The device of claim 10 , wherein the plurality of probe pins are spring-loaded.

14 . The device of claim 9 , wherein the plurality of probe side conductive terminals are couplable to different ones of the plurality of signal side conductive terminals based on a configuration of an electronic component to be tested.

15 . The device of claim 9 , wherein the plurality of testing signals includes at least one of a group consisting of: an analog ground signal, a digital ground signal, a power signal, and an information signal.

16 . The device of claim 9 , further comprising a plurality of contact pads on the interconnect board for coupling to connectors that provide the plurality of testing signals of the test head.

17 . The device of claim 16 , further comprising:

a tester interface; and

a test head coupled to the tester interface, wherein the tester interface conveys the plurality of testing signals between the test head and the contact pads of the interconnect board.

18 . The device of claim 9 , wherein the plurality of interconnects include interconnects that are characterized as one type of a group consisting of: jumpers, switches, dip switches, resistors, wires, solid state relays, electromechanical relays, multiplexer, and receptacles.

19 . A test device comprising:

an interconnect board including:

a probe interface area couplable to a probe head;

a first set of conductive terminals coupled to conductors of the probe interface area;

a second set of conductive terminals coupled to test signal external conductors of the interconnect board to convey signals from a test head;

at least one interconnect configurable to:

couple one conductive terminal in the first set of conductive terminals to one conductive terminal in the second set of conductive terminals during a first test configuration, and

couple the one conductive terminal in the first set of conductive terminals to another conductive terminal in the second set of conductive terminals during a second test configuration, and

couple another conductive terminal in the first set of conductive terminals to the another conductive terminal in the second set of conductive terminals during a third test configuration.

20 . The device of claim 19 , wherein to accommodate testing different configurations of contacts on different semiconductor wafers, different ones of the second set of conductive terminals are couplable to respective probe pin pads in the probe interface area based on a configuration of contacts of a semiconductor wafer to be tested.

Assignments (20)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FILING AND REMOVE APPL. NO. 14085520 REPLACE IT WITH 14086520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Mar 1, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037926/0642 →
CORRECTIVE ASSIGNMENT OF INCORRECT NUMBER 14085520 PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTON OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037785/0568 →
CORRECTIVE ASSIGNMENT OF INCORRECT PATENT APPLICATION NUMBER 14085520 ,PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0399. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037785/0454 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037792/0227 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037879/0581 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 037458 FRAME 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Jan 14, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037515/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 037458 FRAME 0399. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Jan 14, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037515/0390 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FOUNDING, INC.
Reel/Frame 037458/0420 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FOUNDING, INC.
Reel/Frame 037458/0399 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0790 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032445/0577 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032445/0493 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., COLLATERAL AGENT
Reel/Frame 032445/0689 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2013
From: FLYNN, TODD M.; ARGENTO, CHRISTOPHER W.; FAILLACI, STEVEN A.; LEE, THOMAS H.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031797/0301 →