IP Library Granted Patent US 9,009,644
Granted Patent B1
US 9,009,644 · App. 14/136,057 · Granted Apr 14, 2015

Automatic generation of via definitions based on manufacturability

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Quick Facts
Patent No.
US 9,009,644
App. No.
14/136,057
Granted
Apr 14, 2015
Kind
B1
Abstract

A layout system automatically generates via definitions for a routing tool based on manufacturability of vias based on the via definitions. A physical verification tool of the system applies a set of preliminary via definitions to an integrated circuit test design at each of a plurality of offsets from a plurality of via locations to generate a set of candidate via definitions. Candidate via definitions that violate one or more design rules are discarded. A hierarchy constructor tool ranks the resulting candidate via definitions based on a combination of their manufacturability and frequency of applicability in the test design, and a predefined number of the candidate via definitions are selected based on their ranking. These selected via definitions can be used by a routing tool to generate a layout for another (non-test) integrated circuit device.

Claims (50)

1. A computer-implemented method comprising:

applying, at a computer device, a plurality of preliminary via definitions to an integrated circuit test design to identify a set of candidate via definitions;

generating and storing at the computer device data representing a set of selected via definitions based on a comparison of the candidate via definitions to a set of design rules, the set of selected via definitions to be used by a design tool for design of an integrated circuit device; and

generating at the computer device a layout of the integrated circuit device based on the data representing the set of selected via definitions;

wherein generating the data representing the set of selected via definitions comprises:

generating the data representing the set of selected via definitions by ranking the set of candidate via definitions based on a design-for-manufacturability (DFM) characteristic;

wherein ranking the set of candidate via definitions comprises:

identifying, for each of the set of candidate via definitions, a set of offsets where a corresponding preliminary via definition can be used without violating any of the set of design rules; and

ranking the set of candidate via definitions based on the DFM characteristic and the identified set of offsets for each of the set of candidate via locations; and

wherein each of the set of candidate via definitions includes a corresponding preliminary via definition and offset, and herein generating the set of selected via definitions comprises:

establishing a set of links between the preliminary via definitions of the candidate via definitions and their corresponding offsets;

assigning a preliminary weight to each of the set of links based on the corresponding preliminary via definition's corresponding DFM characteristic;

adjusting the preliminary weight of at least one of the set of links based on the preliminary via definition associated with links having the highest total weight to identify a set of adjusted weights; and

generating the set of selected via definitions based on the set of adjusted weights.

2. The method of claim 1 , wherein applying the plurality of preliminary via definitions comprises:

applying a first preliminary via definition of the plurality of preliminary via definitions at a first via location of the test design to generate a first candidate via definition of the set of candidate via definitions; and

applying the first preliminary via definition at a first offset from the first via location to generate a second candidate via definition of the set of candidate via definitions.

3. The method of claim 2 , wherein applying the plurality of preliminary via definitions further comprises:

applying a second preliminary via definition of the plurality of preliminary via definitions at the first via location of the test design to generate a third candidate via definition of the set of candidate via definitions; and

applying the second preliminary via definition at the first offset from the first via location to generate a fourth candidate via definition of the set of candidate via definitions.

4. The method of claim 1 , wherein adjusting the preliminary weight for the at least one of the set of links comprises:

identifying the preliminary via definition associated with links having the highest total weight;

identifying a first set of links connected to the identified preliminary via definition;

identifying a set of offsets connected to the identified first set of links;

identifying a second set of links connected to the set of offsets; and

generating a set of adjusted weights for the second set of links by subtracting the corresponding weight of one of the first set of links from the corresponding weights of the second set of links.

5. A non-transitory computer readable medium embodying a set of executable instructions, the set of executable instructions to manipulate at least one processor to perform a method comprising:

apply a plurality of preliminary via definitions to a test design of a test integrated circuit device to identify a set of candidate via definitions;

generate a set of selected via definitions based on a comparison of the candidate via definitions to a set of design rules, the set of selected via definitions to be used by a design tool for design of an integrated circuit device by:

identifying, for each of the set of candidate via definitions, a set of offsets where the corresponding preliminary via definition can be used without violating any of the set of design rules; and

ranking the set of candidate via definitions based on a design-for-manufacturability (DFM) characteristic and the identified set of offsets for each of the set of candidate via locations, wherein ranking comprises:

identifying, for each of the set of candidate via definitions, a set of offsets where the corresponding preliminary via definition can be used without violating any of the set of design rules; and

ranking the set of candidate via definitions based on the DFM characteristic and the identified set of offsets for each of the set of candidate via locations by:

establishing a set of links between the preliminary via definitions of the candidate via definitions and their corresponding offsets;

assigning a preliminary weight to each of the set of links based on the corresponding preliminary via definition's corresponding DFM characteristic; and

adjusting the preliminary weight of at least one of the set of links based on the preliminary via definition associated with links having the highest total weight to identify a set of adjusted weights; and

generating the set of selected via definitions based on the set of adjusted weights; and

generating a layout of an integrated circuit device based data representing the set of selected via definitions.

6. The computer readable medium of claim 5 , wherein the set of executable instructions is to manipulate the at least one processor to apply the plurality of preliminary via definitions by manipulating the at least one processor to:

apply a first preliminary via definition of the plurality of preliminary via definitions at a first via location of the test design to generate a first candidate via definition of the set of candidate via definitions; and

apply the first preliminary via definition at a first offset from the first via location to generate a second candidate via definition of the set of candidate via definitions.

7. The computer readable medium of claim 6 , wherein the set of executable instructions is to manipulate the at least one processor to apply the plurality of preliminary via definitions by manipulating the at least one processor to:

apply a second preliminary via definition of the plurality of preliminary via definitions at the first via location of the test design to generate a third candidate via definition of the set of candidate via definitions; and

apply the second preliminary via definition at the first offset from the first via location to generate a fourth candidate via definition of the set of candidate via definitions.

8. The computer readable medium of claim 5 , wherein the set of executable instructions is to manipulate the at least one processor to adjust the preliminary weight for the at least one of the set of links by manipulating the processor to:

identify the preliminary via definition associated with links having the highest total weight;

identify a first set of links connected to the identified preliminary via definition;

identify a set of offsets connected to the identified first set of links;

identify a second set of links connected to the set of offsets; and

generate a set of adjusted weights for the second set of links by subtracting the corresponding weight of one of the first set of links from the corresponding weights of the second set of links.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040632 FRAME: 0001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Sep 21, 2017
From: FREESCALE SEMICONDUCTOR INC.
To: NXP USA, INC.
Reel/Frame 044209/0047 →
CHANGE OF NAME Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040632/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FILING AND REMOVE APPL. NO. 14085520 REPLACE IT WITH 14086520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Mar 1, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT OF INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
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CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT OF INCORRECT PATENT APPLICATION NUMBER 14085520 ,PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0399. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037785/0454 →
CORRECTIVE ASSIGNMENT OF INCORRECT NUMBER 14085520 PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTON OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037785/0568 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 037458 FRAME 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Jan 14, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 037458 FRAME 0399. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Jan 14, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
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PATENT RELEASE Recorded Dec 21, 2015
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To: FREESCALE SEMICONDUCTOR, INC.
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From: FREESCALE SEMICONDUCTOR, INC.
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