System for reducing leakage power of electronic circuit
View Patent ↗A system for reducing leakage power of an electronic circuit design, where the circuit design includes multiple timing paths, each timing path made up of multiple cells, using an electronic design automation (EDA) tool. The EDA tool includes a processor that chooses a first replacement cell for replacing a first cell in a first timing path when timing slack is not available in the first path, where a width and threshold voltage of the first replacement cell are greater than a width and threshold voltage of the first cell. The processor then replaces the first cell with the first replacement cell when the overall power consumption of the first replacement cell is less than that of the first cell, and when the timing slack is available for replacing the first cell with the first replacement cell.
1. An electronic design automation (EDA) tool for reducing leakage power of an electronic circuit design, wherein the circuit design includes a plurality of cells interconnected to form a plurality of timing paths, the EDA tool comprising:
a memory that stores the circuit design; and
a processor in communication with the memory, wherein the processor:
selects a first timing path of the plurality of timing paths of the circuit design;
determines availability of timing slack for replacing a first cell in the first timing path;
selects a first replacement cell from a technology library when the timing slack is not available, wherein a type of the first replacement cell is the same as a type of the first cell and a width and threshold voltage of the first replacement cell are greater than the width and threshold voltage of the first cell;
compares an overall power consumption of the first cell and the first replacement cell;
determines availability of timing slack for replacing the first cell with the first replacement cell when the overall power consumption of the first replacement cell is less than the overall power consumption of the first cell; and
replaces the first cell in the circuit design with the first replacement cell based on said determination.
2. The EDA tool of claim 1 , wherein replacing the first cell with the first replacement cell comprises:
replacing the first cell with a first intermediate replacement cell, wherein a type of the first intermediate replacement cell is the same as the type of the first cell and a width of the first intermediate replacement cell is greater than the width of the first cell; and
replacing the first intermediate replacement cell with the first replacement cell, wherein the first replacement cell and the first intermediate replacement cell each have the same type and width, and the threshold voltage of the first replacement cell is greater than a threshold voltage of the first intermediate replacement cell.
3. The EDA tool of claim 1 , wherein the processor further selects a second replacement cell from the technology library when the timing slack is not available for replacing the first cell with the first replacement cell, wherein a type of the second replacement cell is the same as the type of the first replacement cell and a width of the second replacement cell is greater than the width of the first replacement cell.
4. The EDA tool of claim 3 , wherein the processor further:
compares an overall power consumption of the first cell and the second replacement cell;
determines availability of timing slack for replacing the first cell with the second replacement cell when the overall power consumption of the second replacement cell is less than the overall power consumption of the first cell; and
replaces the first cell with the second replacement cell based on said determination of availability of timing slack.
5. The EDA tool of claim 1 , wherein the processor further determines availability of timing slack for replacing a second cell of the first timing path when the overall power consumption of the first replacement cell is greater than the overall power consumption of the first cell.
6. The EDA tool of claim 1 , wherein the processor replaces the first cell with a third replacement cell when the timing slack is available for replacing the first cell, wherein a type of the third replacement cell is the same as the type of the first cell and a threshold voltage of the third replacement cell is greater than the threshold voltage of the first cell.
7. The EDA tool of claim 1 , wherein each of the plurality of cells includes at least one of an AND gate, an OR gate, a NOT gate, a NOR gate, a NAND gate, an XOR gate, an XNOR gate, and a combinational logic cell.
8. A method for reducing leakage power of an electronic circuit design by using an electronic design automation (EDA) tool, wherein the circuit design includes a plurality of timing paths and each timing path includes a plurality of cells, and wherein the EDA tool includes a memory that stores the circuit design and a processor in communication with the memory, the method comprising:
selecting a first timing path of the plurality of timing paths;
determining availability of timing slack for replacing a first cell of the first timing path;
choosing a first replacement cell from a technology library of the EDA tool when the timing slack is not available, wherein a type of the first replacement cell is the same as a type of the first cell and a width and threshold voltage of the first replacement cell are greater than a width and threshold voltage of the first cell;
comparing an overall power consumption of the first cell and the first replacement cell;
determining availability of timing slack for replacing the first cell with the first replacement cell when the overall power consumption of the first replacement cell is less than the overall power consumption of the first cell; and
replacing the first cell with the first replacement cell based on said determination of availability of timing slack for replacing the first cell with the first replacement cell.
9. The method of claim 8 , wherein replacing the first cell with the first replacement cell comprises:
replacing the first cell with a first intermediate replacement cell, wherein a type of the first intermediate replacement cell is the same as the type of the first cell and a width of the first intermediate replacement cell is greater than the width of the first cell; and
replacing the first intermediate replacement cell with the first replacement cell, wherein the first replacement cell and the first intermediate replacement cell each have the same type and width, and the threshold voltage of the first replacement cell is greater than a threshold voltage of the first intermediate replacement cell.
10. The method of claim 8 , further comprising choosing a second replacement cell from the technology library when the timing slack is not available for replacing the first cell with the first replacement cell, wherein a type of the second replacement cell is the same as the type of the first replacement cell and a width of the second replacement cell is greater than the width of the first replacement cell.
11. The method of claim 10 , further comprising:
comparing an overall power consumption of the first cell and the second replacement cell;
determining availability of timing slack for replacing the first cell with the second replacement cell when the overall power consumption of the second replacement cell is less than the overall power consumption of the first cell; and
replacing the first cell with the second replacement cell.
12. The method of claim 8 , further comprising determining availability of timing slack for replacing a second cell in the first timing path when the overall power consumption of the first replacement cell is greater than the overall power consumption of the first cell.
13. The method of claim 8 , further comprising replacing the first cell with a third replacement cell, when the timing slack is available for replacing the first cell, wherein a type of the third replacement cell is the same as the type of the first cell and a threshold voltage of the third replacement cell is greater than the threshold voltage of the first cell.
14. The method of claim 8 , wherein each of the plurality of cells includes at least one of an AND gate, an OR gate, a NOT gate, a NOR gate, a NAND gate, an XOR gate, an XNOR gate, and a combinational logic.