IP Library Patent Application 14069358
Patent Application
App. No. 14/069,358

SENSOR DIE GRID ARRAY PACKAGE

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Quick Facts
Patent No.
US None
App. No.
14/069,358
Abstract

A semiconductor sensor die grid array package includes a semiconductor die having an active surface and an opposite backside surface. The active surface has external die connection pads. Conductive runners respectively connect the die connection pads to external connection mounts of the package. An encapsulant covers the semiconductor die. The encapsulant has a base surface proximal to the conductive runners and a stacking surface opposite the base surface. A sensor die is supported on the stacking surface. The sensor die has an active surface and an opposite backside surface that faces the stacking surface, and the sensor active surface has sensor connection pads. Conductive vias engage with the conductive runners and also are wire bonded to one of the sensor connection pads.

Claims (37)

1 . A sensor die grid array package, comprising:

at least one semiconductor die having an active surface and an opposite other die surface, the active surface having external electrical die connection pads;

conductive runners respectively connecting at least some of the die electrical connection pads to external connection mounts of the package;

an encapsulating material at least partially covering the semiconductor die, the encapsulating material having a base surface proximal to the conductive runners and a stacking surface opposite the base surface;

a sensor supported on the stacking surface, the sensor having a sensor active surface and an opposite sensor surface that faces the stacking surface, the sensor active surface having external electrical sensor connection pads; and

at least one conductive via having a first end and a second end, the first end engaging with one of the conductive runners and the second end being electrically connected to one of the external electrical sensor connection pads with a bond wire.

2 . The sensor die grid array package of claim 1 , further comprising a conductive frame at least partially surrounding the semiconductor die.

3 . The sensor die grid array package of claim 2 , further comprising a lid with a window therein, the lid being mounted directly to the encapsulating material and providing a covering to the sensor active surface, the external electrical sensor connection pads and bond wires.

4 . The sensor die grid array package of claim 3 , wherein the lid is a planar sheet.

5 . The sensor die grid array package of claim 2 , wherein the conductive via is formed from the frame.

6 . The sensor die grid array package of claim 5 , wherein the conductive via is electrically insulated with an insulating material.

7 . The sensor die grid array package of claim 6 , wherein the insulating material is deposited in a recess formed in the frame.

8 . The sensor die grid array package of claim 1 , further comprising a protective covering that covers the sensor active surface, the external electrical sensor connection pads and the bond wire.

9 . The sensor die grid array package of claim 8 , wherein the covering includes a non-electrically conductive gel.

10 . The sensor die grid array package of claim 8 , wherein the covering includes a lid with a window therein.

11 . The sensor die grid array package of claim 10 , wherein the lid has a chamber filled with a non-electrically conductive gel.

12 . A method for assembling a semiconductor sensor die grid array package, comprising:

providing a conductive sheet that has a plurality of frames, each of the frames at least partially surrounding a respective aperture in the sheet, wherein the apertures extend between opposed first and second surfaces of each of the frames;

forming conductive vias in the frames, wherein the vias are exposed at said first surface and extending towards said second surface;

surrounding the vias with an insulating material;

depositing in each aperture at least one semiconductor die, the die having an active surface and an opposite other die surface, the die active surface having external electrical die connection pads;

depositing an encapsulating material in the aperture, the encapsulating material at least partially covering the semiconductor die, the encapsulating material having a base surface proximal to the first surface and a stacking surface opposite the base surface;

removing parts of the frames to expose the vias at the second surface;

electrically connecting the external electrical die connection pads and the vias to conductive runners at least some of which provide external connection mounts of the package;

mounting a sensor on the stacking surface, the sensor having a sensor active surface and an opposite sensor surface that faces the stacking surface, wherein the sensor active surface has external electrical sensor connection pads; and

electrically connecting the external electrical sensor connection pads to respective ones of said vias with bond wires.

13 . The method of claim 12 , further including placing a cover over the sensor active surface, the external electrical sensor connection pads and the bond wires.

14 . The method of claim 13 , wherein the cover includes a non-electrically conductive gel.

15 . The method of claim 14 , wherein the cover includes a lid with a window therein.

16 . The method of claim 12 , wherein the forming the conductive vias includes:

applying a mask to the first surfaces of the frames;

etching one or more recesses in the first surfaces to provide spaced pillars in the frames at exposed regions of the mask; and

depositing an insulating material in the recesses.

17 . The method of claim 12 , wherein the conductive runners are formed using a redistribution layer process resulting in the conductive runners being insulated with an insulating redistribution layer.

18 . The method of claim 17 , wherein the conductive runners are formed from a plated sputter coating.

19 . The method of claim 12 , further including mounting solder balls to a designated external connector contacting area of a respective one of the conductive runners.

20 . The method of claim 12 , further including forming additional conductive runners proximal to the second surface, the additional conductive runners being formed with a redistribution layer process, wherein the additional conductive runners are coupled to respective ones of the vias and selectively attached to ones of the bond wires.

Assignments (18)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FILING AND REMOVE APPL. NO. 14085520 REPLACE IT WITH 14086520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Mar 1, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037926/0642 →
CORRECTIVE ASSIGNMENT OF INCORRECT NUMBER 14085520 PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTON OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037785/0568 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037792/0227 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037879/0581 →
CORRECTIVE ASSIGNMENT OF INCORRECT PATENT APPLICATION NUMBER 14085520 ,PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0399. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037785/0454 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 037458 FRAME 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Jan 14, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037515/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 037458 FRAME 0399. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Jan 14, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037515/0390 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FOUNDING, INC.
Reel/Frame 037458/0399 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FOUNDING, INC.
Reel/Frame 037458/0420 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0790 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., COLLATERAL AGENT
Reel/Frame 032445/0689 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032445/0493 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032445/0577 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2013
From: KALANDAR, NAVAS KHAN ORATTI; MUNIANDY, KESVAKUMAR V.C.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031525/0419 →