Functional path failure monitor
View Patent ↗System circuitry includes a logic circuit having an input and an output that is a functional element of the system circuitry. Pattern application circuitry is coupled to the input of the logic circuit and provides an input pattern to the input of the logic circuit. The input pattern has a valid signature based upon a comparison of the input and the output of the logic circuit when the logic circuit is functioning properly. A logic comparator is coupled to the input and the output of the logic circuit and generates pulses in response to the input pattern. A counter is coupled to the logic comparator that obtains a count of the pulses generated by the logic comparator in response to the input pattern. A signature comparator is coupled to the counter and generates a warning signal if the valid signature is different from the count.
1. System circuitry, comprising:
a logic circuit having an input and an output that is a functional element of the system circuitry;
pattern application circuitry coupled to the input of the logic circuit that provides an input pattern to the input of the logic circuit, wherein the input pattern has a valid signature based upon a comparison of the input and the output of the logic circuit when the logic circuit is functioning properly;
a logic comparator coupled to the input and the output of the logic circuit that generates pulses in response to the input pattern;
a counter coupled to the logic comparator that obtains a count of the pulses generated by the logic comparator in response to the input pattern; and
a signature comparator coupled to the counter that generates a warning signal if the valid signature is different from the count.
2. The system circuitry of claim 1 , further comprising a delay circuit between the output of the logic circuit and the logic comparator, wherein the warning signal indicates an imminent failure of the logic circuit.
3. The system circuitry of claim 2 , wherein the logic circuit comprises a plurality of logic gates having an output coupled to the delay circuit.
4. The system circuitry of claim 3 , wherein the system circuitry further comprises a flip-flop having an input coupled to the output of the plurality of logic gates and an output for use by the system circuitry.
5. The system circuitry of claim 4 , wherein a delay of the delay circuit is programmable.
6. The system circuitry of claim 1 , further comprising a timer coupled to the counter to indicate a start and stop of the counter in order to obtain the count.
7. The system circuitry of claim 1 , wherein the logic circuit comprises a plurality of logic gates and a flip-flop, wherein an output of the flip-flop is the output of the logic circuit and the warning signal indicates an actual failure of the logic circuit.
8. The system circuitry of claim 1 , wherein the logic comparator comprises:
an AND circuit and a first flip-flop having an output coupled to the counter; and
a second flip-flop coupled to the input of the logic circuit;
wherein the first and second flip-flops are clocked by a clock signal.
9. The system circuitry of claim 8 , wherein the logic circuit comprises a plurality of logic gates and a third flip-flop having an output, wherein the output of the third flip-flop is the output of the logic circuit and the third flip-flop is clocked by the clock signal.
10. The system circuitry of claim 8 , wherein the logic circuit comprises a plurality of logic gates having an output as the output of the logic circuit and the system circuitry further comprises a third flip-flop coupled to the output of the logic gates, wherein the third flip-flop is clocked by the clock signal.
11. A method of operating system circuitry, comprising:
using a logic circuit having an input and an output as a functional element of the system circuitry;
providing an input pattern to the input of the logic circuit, wherein the input pattern has a valid signature based upon a comparison of the input and the output of the logic circuit when the logic circuit is functioning properly;
generating pulses in response to the input and the output of the logic circuit when the logic circuit receives the input pattern; and
counting the pulses generated in response to the input pattern to provide a count; and
generating a warning signal if the valid signature is different from the count.
12. The method of claim 11 , wherein the generating the pulses is further characterized by adding delay to the output of the logic circuit, wherein the warning signal indicates an imminent failure of the logic circuit.
13. The system circuitry of claim 12 , wherein the using the logic circuit is further characterized by the logic circuit comprising a plurality of logic gates having an output as the output of the logic circuit and the adding delay is further characterized by adding delay to the output of the logic gates.
14. The method of claim 13 , further comprising using a flip-flop having an input coupled to the output of the plurality of logic gates and an output.
15. The method of claim 14 , wherein the adding delay is further characterized by the delay being programmable.
16. The method of claim 11 , wherein the using the logic circuit is further characterized by the logic circuit further comprising a plurality of logic gates and a flip-flop, wherein an output of the flip-flop is the output of the logic circuit.
17. The method of claim 11 , wherein:
the providing an input pattern to the input of the logic circuit uses a first flip-flop clocked by a clock signal; and
the generating pulses uses a second flip-flop clocked by the clock signal.
18. The system circuitry of claim 17 , wherein the using the logic circuit is further characterized by the logic circuit comprising a plurality of logic gates and a third flip-flop having an output, wherein the output of the third flip-flop is the output of the logic circuit and the third flip-flop is clocked by the clock signal.
19. The system circuitry of claim 17 , wherein the using the logic circuit is further characterized by the logic circuit comprising a plurality of logic gates having an output as the output of the logic circuit and the system circuitry further comprises a third flip-flop coupled to the output of the logic gates, wherein the third flip-flop is clocked by the clock signal.
20. System circuitry, comprising:
a logic circuit having a critical path between an input and an output;
pattern application circuitry coupled to the input of the logic circuit that provides an input pattern to the input of the logic circuit, wherein the input pattern has a valid signature based upon a comparison of the input and the output of the logic circuit when the logic circuit is functioning properly;
a logic comparator coupled to the critical path that generates pulses in response to the logic circuit receiving the input pattern;
a counter coupled to the logic comparator that obtains a count of the pulses generated by the logic comparator in response to the logic circuit receiving the input pattern; and
a signature comparator coupled to the counter that generates a warning signal if the valid signature is different from the count, wherein the warning signal indicates one of group consisting of an imminent failure and an actual failure.