Monitoring system for detecting degradation of integrated circuit
View Patent ↗A monitoring system for detecting stress degradation of a semiconductor integrated circuit has an amplifier circuit and degradation test transistors. Multiplexers are provided that have an output coupled to a respective electrode of the degradation test transistor. Each of the multiplexers has an input coupled to one of the monitor nodes and a respective node of the amplifier circuit. In operation, the multiplexers selectively insert the degradation test transistor into either the integrated circuit or the amplifier circuit so that when inserted into the integrated circuit the degradation test transistor is subjected to stress degradation voltages in the integrated circuit. When the degradation test transistor is inserted into the amplifier circuit, an output signal is generated that is indicative of stress degradation of the integrated circuit.
1. A system for detecting stress degradation of a semiconductor circuit, the system comprising:
a primary semiconductor circuit that has a plurality of monitor nodes;
an amplifier circuit with at least one amplifier output terminal;
at least one degradation test transistor; and
a plurality of multiplexers each having an output coupled to a respective electrode of the degradation test transistor, and each of the multiplexers having an input coupled to one of the monitor nodes and a respective node of the amplifier circuit,
wherein in operation the multiplexers selectively insert the degradation test transistor into either the primary semiconductor circuit or the amplifier circuit so that when inserted into the primary semiconductor circuit the degradation test transistor is subjected to stress degradation voltages in the primary semiconductor circuit and wherein when inserted into the amplifier circuit an output signal at the output terminal is indicative of stress degradation of the primary semiconductor circuit,
wherein the amplifier circuit includes a differential amplifier and the degradation test transistor forms part of a first branch of the differential amplifier and part of a second branch of the differential amplifier is formed by a reference transistor.
2. The system for detecting stress degradation of claim 1 , wherein the differential amplifier is one of a plurality of cascaded differential amplifiers, each of the differential amplifiers including a said degradation test transistor and a said reference transistor.
3. The system for detecting stress degradation of claim 2 , wherein there are a plurality of switches that in operation selectively isolate each said reference transistor from the amplifier circuit when said degradation test transistor is inserted into the primary semiconductor circuit.
4. The system for detecting stress degradation of claim 2 , wherein in operation the supply voltage across each said reference transistor is reduced when said degradation test transistor is inserted into the primary semiconductor circuit.
5. The system for detecting stress degradation of claim 2 , wherein the least one amplifier output terminal includes differential output nodes of the cascaded differential amplifiers.
6. The system for detecting stress degradation of claim 1 , further including a processor for providing control signals for controlling when said degradation test transistor is inserted into the primary semiconductor circuit.
7. The system for detecting stress degradation of claim 6 , wherein an input of the processor is coupled to the output terminal.
8. The system for detecting stress degradation of claim 1 , wherein the primary semiconductor circuit and at least part of the amplifier circuit are formed on a single semiconductor substrate.
9. The system for detecting stress degradation of claim 1 , wherein the monitor nodes are gate, drain and source electrodes of a transistor.
10. The system for detecting stress degradation of claim 1 , wherein the monitor nodes are coupled to the amplifier circuit via unity gain buffers.
11. A method for monitoring stress degradation of a semiconductor circuit, the method being controlled by a processor, the method comprising:
inserting at least one degradation test transistor into a primary semiconductor circuit to thereby subject the degradation test transistor to stress degradation voltages;
removing the degradation test transistor from the primary semiconductor circuit;
inserting the degradation test transistor into an amplifier circuit;
analyzing an output signal at an output terminal of the amplifier circuit to determine if the degradation test transistor is degraded;
providing a warning signal indicative of the primary semiconductor circuit being degraded in response to the analyzing determining that the degradation test transistor is degraded; and
reconfiguring the primary semiconductor circuit when the warning signal is provided.
12. A method for monitoring stress degradation of claim 11 , further including removing a power supply from the primary semiconductor circuit when the warning signal is provided.
13. The method for monitoring stress degradation of claim 11 , wherein the amplifier circuit includes a differential amplifier circuit.
14. The method for monitoring stress degradation of claim 13 , further comprising a reference transistor, wherein the degradation test transistor forms a first branch of the differential amplifier and the reference transistor forms a second branch of the differential amplifier.
15. The method for monitoring stress degradation of claim 14 , wherein a supply voltage across said reference transistor is reduced when said degradation test transistor is inserted into the primary semiconductor circuit.
16. The method for monitoring stress degradation of claim 14 , wherein there are a plurality of switches that in operation selectively isolate the reference transistor from the amplifier circuit when the degradation test transistor is inserted into the primary semiconductor circuit.