Method of gate strapping in split-gate memory cell with inlaid gate
View Patent ↗A process integration is disclosed for fabricating non-volatile memory (NVM) cells having patterned select gates ( 211, 213 ), charge storage layers ( 219 ), inlaid control gates ( 223, 224 ), and inlaid control gate contact regions ( 228 ).
1. A semiconductor fabrication process comprising:
forming a first select gate structure and one or more sacrificial structures over the semiconductor substrate, where the one or more sacrificial structures are spaced apart from the first select gate structure on a first side to form a control gate opening, and where the one or more sacrificial structures are positioned in relation to the first select gate structure to define a control gate contact opening;
forming a charge storage layer on at least a top and sidewall surface of the first select gate structure and on a bottom surface of the control gate opening; and
simultaneously forming an inlaid control gate in the control gate opening and an inlaid control gate contact layer in the control gate contact opening as a continuous conductive layer by forming a planarized conductive layer on the charge storage layer to fill the control gate opening and control gate contact opening.
2. The semiconductor fabrication process of claim 1 , further comprising:
selectively removing at least part of the one or more sacrificial structures to expose intended source and/or drain regions of the semiconductor substrate; and
implanting the intended source and/or drain regions with one or more implantation steps to form source and/or drain regions in the semiconductor substrate.
3. The semiconductor fabrication process of claim 1 , where forming the first select gate structure and one or more sacrificial structures comprises:
forming one or more gate dielectric layers on the semiconductor substrate;
forming a polysilicon layer on the one or more gate dielectric layers to cover the semiconductor substrate; and
patterning the polysilicon layer and one or more gate dielectric layers to form the first select gate structure with a first patterned polysilicon layer and to form the one or more sacrificial structures with one or more additional patterned polysilicon layers comprising:
a first additional patterned polysilicon layer that is laterally spaced apart from the first select gate structure on the first side to form the control gate opening, and
a second additional patterned polysilicon layer that is orthogonally spaced apart from a peripheral end of the first additional patterned polysilicon layer to form the control gate contact opening.
4. The semiconductor fabrication process of claim 3 , where the control gate contact opening is formed at a peripheral end of a non-volatile memory array.
5. The semiconductor fabrication process of claim 3 , where the control gate contact opening is formed at an interior position of a non-volatile memory array.
6. The semiconductor fabrication process of claim 1 , where forming the first select gate structure and one or more sacrificial structures comprises:
forming a plurality of patterned select gate electrodes on the semiconductor substrate;
forming a planarized dielectric layer over the semiconductor substrate which exposes an upper surface of the plurality of patterned select gate electrodes;
patterning the planarized dielectric layer to protect the plurality of patterned select gate electrodes and form the one or more sacrificial structures comprising:
a first patterned dielectric layer that is laterally spaced apart from the first select gate structure on the first side to form the control gate opening, and
a second patterned dielectric layer that is orthogonally spaced apart from a peripheral end of the first patterned dielectric layer to form the control gate contact opening.
7. The semiconductor fabrication process of claim 6 , where the control gate contact opening is formed at a peripheral end of a non-volatile memory array.
8. The semiconductor fabrication process of claim 6 , where the control gate contact opening is formed at an interior position of a non-volatile memory array.
9. The semiconductor fabrication process of claim 1 , where forming the charge storage layer comprises forming a nanocrystal stack to cover the top and sidewall surfaces of the first select gate structure and the bottom surface of the control gate opening.
10. The semiconductor fabrication process of claim 1 , where simultaneously forming the inlaid control gate and inlaid control gate contact layer comprises:
depositing a barrier metal layer and a polysilicon layer to completely fill the control gate opening and control gate contact opening; and
polishing the polysilicon layer and barrier metal layer to form the inlaid control gate in the control gate opening and the inlaid control gate contact layer in the control gate contact opening as a continuous conductive layer.
11. A method of forming a memory cell comprising an inlaid control gate and an inlaid control gate contact, comprising:
forming a select gate structure and a sacrificial structure over a semiconductor substrate, where the sacrificial structure is spaced apart from the select gate structure on a first side to form a control gate opening, and where the sacrificial structure is positioned in relation to the select gate structure to define a control gate contact opening;
lining the control gate opening with a charge storage layer comprising a plurality of discrete storage elements; and
depositing a conductive layer on the charge storage layer to fill the control gate opening and the control gate contact opening;
planarizing the conductive layer to form the inlaid control gate in the control gate opening and the inlaid control gate contact in the control gate contact opening;
removing the sacrificial structure with a selective etch while protecting the inlaid control gate and inlaid control gate contact with one or more etch mask layers;
forming a source in the semiconductor substrate adjacent to the inlaid control gate; and
forming a drain in the semiconductor substrate adjacent to the select gate structure.
12. The method of claim 11 , where forming the select gate structure and sacrificial structure comprises using a single masking step which lithographically defines (i) a gate length and width of the select gate structure, (ii) a gate length of an inlaid control gate yet to be formed, and (iii) a strap gap distance D STRAP of an inlaid control gate contact yet to be formed.
13. The method of claim 11 , where forming the select gate structure and sacrificial structure comprises forming a second sacrificial structure over a drain area of the semiconductor substrate adjacent to the select gate structure; and removing the second sacrificial structure prior to forming the drain in the semiconductor substrate.
14. The method of claim 11 , where forming the select gate structure and sacrificial structure comprises:
forming one or more gate dielectric layers on the semiconductor substrate;
forming a polysilicon layer on the one or more gate dielectric layers; and
patterning the polysilicon layer and one or more gate dielectric layers to form the select gate structure with a first patterned polysilicon layer and to form the sacrificial structure with one or more additional patterned polysilicon layers comprising:
a first additional patterned polysilicon layer that is laterally spaced apart from the select gate structure on the first side to form the control gate opening, and
a second additional patterned polysilicon layer that is orthogonally spaced apart from a peripheral end of the first additional patterned polysilicon layer to form the control gate contact opening.
15. The method of claim 14 , where the control gate contact opening is formed at a peripheral end of a non-volatile memory array.
16. The method of claim 14 , where the control gate contact opening is formed at an interior position of a non-volatile memory array.
17. The method of claim 11 , where forming the select gate structure and sacrificial structure comprises:
forming a pair of patterned select gate structures on the semiconductor substrate;
forming a planarized dielectric layer over the semiconductor substrate where an upper surface of the pair of patterned select gate structures is exposed; and
patterning the planarized dielectric layer to protect the pair of patterned select gate structures and form the sacrificial structure comprising:
a first patterned dielectric layer that is laterally spaced apart from the select gate structure on the first side to form the control gate opening, and
a second patterned dielectric layer that is orthogonally spaced apart from a peripheral end of the first patterned dielectric layer to form the control gate contact opening.
18. A semiconductor device, comprising:
a semiconductor substrate;
a non-volatile polysilicon discrete storage element split-gate bitcell array formed on the semiconductor substrate surface, comprising:
a plurality of select gate electrodes disposed in a parallel pattern over the semiconductor substrate;
a plurality of charge storage structures, each comprising a plurality of discrete storage elements and disposed adjacent to at least a sidewall surface of a corresponding select gate electrode and to extend over a control channel region in the semiconductor substrate adjacent to the corresponding select gate electrode;
a plurality of inlaid control gate electrodes, each disposed adjacent to a corresponding charge storage structure located on a sidewall surface of a corresponding select gate electrode; and
one or more inlaid control gate contacts formed with the plurality of inlaid control gate electrodes as a continuous conductive layer.
19. The semiconductor device of claim 18 , where the plurality of inlaid control gate electrodes and one or more inlaid control gate contacts are formed with planarized polysilicon.
20. The semiconductor device of claim 18 , where the one or more inlaid control gate contacts are formed as strapped or end cell contacts.