Analog-to-digital converter with clock halting circuit
View Patent ↗An analog to digital converter (ADC) includes a clock-halting circuit that is enabled by an externally generated trigger signal. The clock-halting circuit halts an input clock signal to the ADC for a predetermined time period and resumes the input clock signal to the ADC when the predetermined time period ends.
1. A system for converting an analog signal into a digital signal, comprising:
an analog-to-digital converter (ADC) having an input terminal for receiving the analog signal, a clock input terminal for receiving an input clock signal, and an output terminal for outputting the digital signal; and
a clock-halting circuit, connected to the clock input terminal of the ADC, for halting the input clock signal to the ADC based on an external trigger signal, wherein the trigger signal toggles between logic high and low states, and wherein the clock-halting circuit includes:
a synchronizer having an input terminal for receiving the trigger signal, a clock input terminal for receiving the input clock signal, and an output terminal for outputting a synchronous trigger signal;
a counter circuit having an input terminal connected to the output terminal of the synchronizer for receiving the synchronous trigger signal and a clock input terminal for receiving the input clock signal, wherein the counter circuit starts a count of a predetermined set of count values after the trigger signal toggles between the logic high and low states, and wherein the predetermined set of count values corresponds to a predetermined time period; and
a clock-halting latch, connected between the counter circuit and the clock input terminal of the ADC, for halting the input clock signal to the ADC for the predetermined time period.
2. The system of claim 1 , wherein the counter circuit comprises:
a D flip-flop having an input terminal connected to the output terminal of the synchronizer for receiving the synchronous trigger signal, a clock input terminal for receiving the input clock signal, and an output terminal;
a first logic gate having first and second input terminals connected to the output terminals of the synchronizer and the D flip-flop, respectively, and an output terminal for outputting a counter start signal;
first and second counters each having an input terminal connected to the output terminal of the first logic gate for receiving the counter start signal, a clock input terminal for receiving the input clock signal, and an output terminal for outputting respective first and second sets of count values that initiate the count of the predetermined set of count values;
second and third logic gates connected to the output terminals of the first and second counters for receiving the first and second sets of count values, respectively, and generating first and second output signals;
a fourth logic gate having first and second input terminals connected to the second and third logic gates for receiving the first and second output signals and generating a clock halting signal; and
a fifth logic gate having a first input terminal connected to the fourth logic gate for receiving the clock halting signal, a second input terminal for receiving the input clock signal, and an output terminal connected to the clock input terminals of the first and second counters for gating the input clock signal upon completion of the predetermined time period.
3. The system of claim 2 , wherein the first, second, third, fourth, and fifth logic gates each comprise at least one of an OR gate and an AND gate.
4. The system of claim 2 , wherein the first and second counters each comprise at least one of a positive and a negative edge trigger counter.
5. The system of claim 1 , wherein the clock-halting latch has an input terminal that receives the input clock signal, a clock input terminal that receives the clock halting signal, and an output terminal connected to the clock input terminal of the ADC that outputs the clock halting signal during the predetermined time period.
6. The system of claim 1 , wherein the synchronizer comprises a dual-edge triggered flip-flop.
7. The system of claim 1 , wherein the trigger signal is received from a noise source.
8. The system of claim 7 , wherein the noise source comprises a switched-mode power supply (SMPS).
9. An integrated circuit, comprising:
a switched-mode power supply (SMPS), for receiving an external unregulated supply voltage and generating a regulated voltage, wherein the SMPS includes:
a control circuit for generating a trigger signal to control switching of a switching element;
an analog-to-digital converter (ADC) having an input terminal for receiving an analog signal, a clock input terminal for receiving an input clock signal, and an output terminal for outputting a digital signal; and
a clock-halting circuit, connected between the ADC and the SMPS, for receiving the trigger signal and halting the input clock signal to the ADC, wherein the clock-halting circuit includes:
a synchronizer having an input terminal connected to the control circuit for receiving the trigger signal, a clock input terminal for receiving the input clock signal, and an output terminal for outputting a synchronous trigger signal;
a counter circuit having an input terminal connected to the output terminal of the synchronizer for receiving the synchronous trigger signal and a clock input terminal for receiving the input clock signal, wherein the counter circuit, when triggered by the synchronous trigger signal, starts a count of a predetermined set of count values, wherein the predetermined set of count values corresponds to a predetermined time period; and
a clock-halting latch, connected to the counter circuit and the clock input terminal of the ADC, for halting the input clock signal for the predetermined time period.
10. The integrated circuit of claim 9 , wherein the counter circuit comprises:
a D flip-flop having an input terminal connected to the output terminal of the synchronizer for receiving the synchronous trigger signal, a clock input terminal for receiving the input clock signal, and an output terminal for outputting the synchronous trigger signal;
a first logic gate having first and second input terminals connected to the output terminals of the synchronizer and the D flip-flop, respectively, for receiving the synchronous trigger signal, and an output terminal for outputting a counter start signal;
first and second counters each having an input terminal connected to the output terminal of the first logic gate for receiving the counter start signal, a clock input terminal for receiving the input clock signal, and an output terminal for outputting first and second sets of count values;
second and third logic gates connected to the output terminals of the first and second counters for receiving the first and second set of count values, respectively, and generating first and second output signals;
a fourth logic gate having first and second input terminals connected to the second and third logic gates, for receiving the first and second output signals and generating a clock halting signal;
a fifth logic gate having a first input terminal connected to the fourth logic gate for receiving the clock halting signal, a second input terminal for receiving the input clock signal, and an output terminal connected to the clock input terminals of the first and second counters for gating the input clock signal to the first and second counters upon completion of the predetermined time period.
11. The integrated circuit of claim 10 , wherein the first, second, third, fourth, and fifth logic gates each comprise at least one of an OR gate and an AND gate.
12. The integrated circuit of claim 10 , wherein the first and second counters each comprise at least one of a positive and a negative edge triggered counter.
13. The integrated circuit of claim 9 , wherein the clock-halting latch has an input terminal that receives the input clock signal, a clock input terminal that receives the clock halting signal, and an output terminal, connected to the clock input terminal of the ADC, that outputs the clock halting signal during the predetermined time period.
14. The integrated circuit of claim 9 , wherein the synchronizer comprises a dual-edge triggered flip-flop.