IP Library Granted Patent US 9,082,493
Granted Patent B2
US 9,082,493 · App. 14/069,195 · Granted Jul 14, 2015

Adaptive erase methods for non-volatile memory

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Quick Facts
Patent No.
US 9,082,493
App. No.
14/069,195
Granted
Jul 14, 2015
Kind
B2
Abstract

A method includes an erase of a plurality of blocks of memory cells in which the memory cells within a block are simultaneously erased. The erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times. The erase pulse is applied to the plurality of blocks in parallel. An erase verify is performed after each application of the erase pulse. After a number applications of the erase pulse, it is determined if a condition comprising one of a group consisting of any memory cell has been more erased than a first predetermined amount and any memory cell has been erased less than a second predetermined amount has been met. If the condition has been met, erasing is continued by applying the erase pulse to the block having the memory cell with the condition independently of the other blocks of the plurality of blocks.

Claims (39)

1. A method of performing an erase of a plurality of blocks of memory cells, wherein the memory cells within a block are simultaneously erased and an erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times, the method comprising:

applying the erase pulse to the plurality of blocks in parallel and performing an erase verify after each application of the erase pulse;

after a predetermined number applications of the erase pulse, determining if a condition comprising any memory cell has been more erased than a first predetermined amount; and

if the determining finds the condition has been met, continue erasing by applying the erase pulse to the block having the memory cell with the condition independently of other blocks of the plurality of blocks.

2. The method of claim 1 , wherein the continue erasing is further characterized by applying the erase pulse to each block independently of the other blocks.

3. The method of claim 2 , wherein the continue erasing is performed serially on the plurality of blocks.

4. The method of claim 1 , wherein the condition comprises a memory cell having been erased more than the first predetermined amount which is indicated by the cell having threshold voltage below a first predetermined limit.

5. The method of claim 1 , wherein a second condition comprises a memory cell having been erased less than a second predetermined amount which is indicated by the cell having threshold voltage above a second predetermined limit.

6. The method of claim 1 , wherein the performing the erase further comprises performing a soft program operation after all of the memory cells have passed an erase verify.

7. The method of claim 6 , wherein the performing the soft program operation ensures that all of the memory cells are erased between a predetermined minimum amount of erasing and a predetermined maximum amount of erasing.

8. The method of claim 1 , wherein the performing the erase further comprises performing a pre-program operation prior to applying the erase pulse.

9. The method of claim 1 , wherein the method includes performing an erase of a second plurality of blocks of memory cells, further comprising:

applying the erase pulse to the second plurality of blocks in parallel and performing an erase verify after each application of the erase pulse;

after a predetermined number of applications of the erase pulse to the second plurality of blocks, determining if a second condition comprising one of a group consisting of any memory cell in the second plurality of blocks has been more erased than a first predetermined amount and any memory cell in the second plurality of blocks has been erased less than a second predetermined amount has been met; and

if the determining finds the second condition has been met, continue erasing by applying the erase pulse to the block in the second plurality having the memory cell with the second condition independently of the other blocks in the second plurality of blocks.

10. The method of claim 9 , wherein the applying the erase pulse is further characterized by the erase pulse having a predetermined voltage and duration.

11. A method of performing an erase of a plurality of blocks of memory cells, wherein the memory cells within a block are simultaneously erased and the erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times, the method comprising:

applying the erase pulse to the plurality of blocks in parallel and performing an erase verify after each application of the erase pulse;

after a predetermined number applications of the erase pulse, determining if any memory cell has been more erased than a first predetermined amount; and

if a memory cell has been erased more than the first predetermined amount, continue erasing by applying the erase pulse to the block having the memory cell that has been erased more than the first predetermined amount independently of the other blocks of the plurality of blocks.

12. The method of claim 11 , further comprising:

after the predetermined number applications of the erase pulse, determining if any memory cell has been erased less than a second predetermined amount; and

if a memory cell has been erased less than the second predetermined amount, continue erasing by applying the erase pulse to the block having the memory cell that has been erased less than the second predetermined amount independently of the other blocks of the plurality of blocks.

13. The method of claim 12 , wherein the continue erasing by applying the erase pulse to the block having the memory cell that has been erased more than the first predetermined amount is further characterized as applying the erase pulse to each block of the plurality of blocks independently of the other blocks.

14. The method of claim 13 , wherein the continue erasing by applying the erase pulse to the block having the memory cell that has been erased less than the second predetermined amount is further characterized as applying the erase pulse to each block of the plurality of blocks independently of the other blocks.

15. The method of claim 14 , further comprising continuing erasing by applying the erase pulse to the plurality of blocks in parallel and performing an erase verify after each application of the erase pulse if none of the memory cells have a condition comprising one of a group consisting of having been erased less than the second predetermined amount and having been more erased than the first predetermined amount.

16. A method of performing an erase of a plurality of blocks of memory cells, wherein the memory cells within a block are simultaneously erased and the erase of each block of the plurality of blocks is performed using an erase pulse applied multiple times, the method comprising:

applying the erase pulse to the plurality of blocks in parallel and performing an erase verify after each application of the erase pulse;

after a predetermined number applications of the erase pulse, determining if any memory cell has been less erased than a first predetermined amount;

if a memory cell has been erased less than the first predetermined amount, continue erasing by applying the erase pulse to the block having the memory cell that has been erased less than the first predetermined amount independently of the other blocks of the plurality of blocks; and

after the predetermined number applications of the erase pulse, determining if any memory cell has been erased more than a second predetermined amount;

if a memory cell has been erased more than the second predetermined amount, continue erasing by applying the erase pulse to the block having the memory cell that has been erased more than the second predetermined amount independently of the other blocks of the plurality of blocks; and

continue applying the erase pulse to the plurality of blocks in parallel and performing an erase verify after each application of the erase pulse if none of the memory cells have been erased more than the second predetermined amount or less than the second predetermined amount.

17. The method of claim 16 , wherein the continue erasing by applying the erase pulse to the block having the memory cell that has been erased less than the first predetermined amount is further characterized as applying the erase pulse to each block of the plurality of blocks independently of the other blocks.

18. The method of claim 16 , further comprising performing pre-programming before applying the erase pulse and soft programming after erasing all of the memory cells have passed an erase verify.

19. The method of claim 16 , wherein the method includes performing an erase of a second plurality of blocks of memory cells, further comprising:

applying the erase pulse to the second plurality of blocks in parallel;

after a predetermined number of applications of the erase pulse to the second plurality of blocks, determining if a second condition comprising one of a group consisting of any memory cell in the second plurality has been more erased than a first predetermined amount and any memory cell in the second plurality has been erased less than a second predetermined amount has been met; and

if the determining finds the second condition has been met, continue erasing by applying the erase pulse to the block in the second plurality of blocks having the memory cell with the second condition independently of the other blocks in the second plurality of blocks.

Assignments (21)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
MERGER Recorded Jan 3, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041144/0363 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FILING AND REMOVE APPL. NO. 14085520 REPLACE IT WITH 14086520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Mar 1, 2016
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CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
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CORRECTIVE ASSIGNMENT OF INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
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CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 037458 FRAME 0399. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Jan 14, 2016
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