Body bias control circuit
View Patent ↗A body bias control circuit including an output coupled to provide a bias voltage to a body terminal. The body bias control circuit is configured to change the bias voltage from a first bias voltage to a second bias voltage over a period of time in which a magnitude of an effective rate of change of the bias voltage varies over the period of time. For voltages between the first and second bias voltages closer to a source voltage, the magnitude of the effective rate of change is smaller than for bias voltages between the first and second bias voltages further from the source voltage.
1. A circuit, comprising:
a transistor including a body terminal coupled to receive a bias voltage, and a source terminal coupled to receive a source voltage; and
a body bias control circuit including an output coupled to provide the bias voltage to the body terminal, wherein the body bias control circuit is configured to change the bias voltage from a first bias voltage to a second bias voltage over a period of time in which a magnitude of an effective rate of change of the bias voltage varies over the period of time wherein for bias voltages between the first and second bias voltages closer to the source voltage, the magnitude of the effective rate of change is smaller than for bias voltages between the first and second bias voltages further from the source voltage.
2. The circuit of claim 1 , wherein the magnitude of the effective rate of change of the bias voltage increases over the period of time.
3. The circuit of claim 1 , wherein a moving average of the bias voltage changes in a quadratic manner over the period of time.
4. The circuit of claim 1 , wherein the transistor is an n-type transistor formed in a Pwell, and the second bias voltage is less than the first bias voltage.
5. The circuit of claim 1 , wherein the transistor is a p-type transistor formed in an Nwell, and the second bias voltage is greater than the first bias voltage.
6. The circuit of claim 1 , wherein the body bias control circuit is configured to change the bias voltage from the first bias voltage to the second bias voltage by applying at the output, each for a corresponding time duration, a series of bias target level voltages in between the first bias voltage and the second bias voltage.
7. The circuit of claim 6 , wherein each corresponding time duration is a same time duration.
8. The circuit of claim 6 , wherein the body bias control circuit comprises a charge pump used for pulling the output towards each of the series of bias target level voltages and the second bias voltage.
9. The circuit of claim 6 , wherein the body bias control circuit comprises:
a plurality of taps, each tap of the plurality corresponding to a bias target level voltage of the series of bias target level voltages, and
a tap controller configured to select taps of the plurality of taps, for changing the bias voltage from the first bias voltage to the second bias voltage.
10. The circuit of claim 1 wherein the body bias control circuit is configured to change the bias voltage from the second bias voltage to the first bias voltage over a second period of time in which a magnitude of a second effective rate of change of the bias voltage varies over the second period of time wherein for the bias voltages between the second and first bias voltages closer to the source voltage, the magnitude of the second effective rate of change is smaller than for the bias voltages between the second and first bias voltages further from the source voltage.
11. A method for controlling a body bias voltage, comprising:
providing a bias voltage to a body terminal of a transistor and a source voltage to a source terminal of the transistor;
changing the bias voltage from a first bias voltage to a second bias voltage over a period of time in which a magnitude of an effective rate of change of the bias voltage varies over the period of time, wherein for bias voltages between the first and second bias voltages closer to the source voltage, the magnitude of the effective rate of change is smaller than for bias voltages between the first and second bias voltages further from the source voltage.
12. The method of claim 11 , wherein the changing the bias voltage from the first bias voltage to the second bias voltage is performed such that the magnitude of the effective rate of change of the bias voltage increases over the period of time.
13. The method of claim 11 , wherein the changing the bias voltage from the first bias voltage to the second bias voltage is performed such that a moving average of the bias voltage changes in a quadratic manner over the period of time.
14. The method of claim 11 , wherein the transistor is an n-type transistor formed in a P well, and the second bias voltage is less than the first bias voltage.
15. The method of claim 11 , wherein the transistor is a p-type transistor formed in an Nwell, and the second bias voltage is greater than the first bias voltage.
16. The method of claim 11 further comprising:
changing the bias voltage from the second bias voltage to the first bias voltage over a second period of time in which a magnitude of a second effective rate of change of the bias voltage varies over the second period of time, wherein for the bias voltages between the second and first bias voltages closer to the source voltage, the magnitude of the second effective rate of change is smaller than for the bias voltages between the second and first bias voltages further from the source voltage.
17. A circuit, comprising:
a transistor including a body terminal coupled to receive a bias voltage, and a source terminal coupled to receive a source voltage; and
a body bias control circuit including an output coupled to provide the bias voltage to the body terminal, wherein the body bias control circuit is configured to sequentially step at different target levels, the bias voltage from a starting bias voltage to an ending bias voltage over a period of time in which voltage step sizes between the different target levels vary over the period of time, wherein a voltage step size between target levels closer to the source voltage is smaller than a voltage step size between target levels further from the source voltage.
18. The circuit of claim 17 , wherein a size of each voltage step between the target levels increases over the period of time.
19. The circuit of claim 17 , wherein a size of each voltage step between the target levels varies in a quadratic manner over the period of time.
20. The circuit of claim 17 , wherein the body bias control circuit comprises:
a charge pump;
a plurality of taps coupled to the charge pump, each tap of the plurality of taps corresponding to a target level of the different target levels of the bias voltage; and
a tap controller configured to select a tap of the plurality of taps corresponding to a target level of the different target levels.