Watchpoint support system for functional simulator
View Patent ↗A functional simulator with watchpoint support includes a CPU having a first-level DMI cache, a watchpoint manager having a second-level DMI cache, an interconnect module, and a memory controller. The simulator is operated by a front-end tool. Watchpoints corresponding to a predetermined memory addresses are set by the front-end tool and stored as a watchpoint address list in the watchpoint manager. When a memory access request is received by the first-level DMI cache, after a failure to complete the memory access request, the CPU transmits the request to the watchpoint manager. The watchpoint manager searches for a memory address associated with the memory access request in the watchpoint address list. If a match is found, the watchpoint manager generates a watchpoint hit signal and notifies the front-end tool.
1. A functional simulator with watchpoint support and operated by a front-end tool, the functional simulator comprising:
a central processing unit (CPU) including a first-level direct memory interface (DMI) cache for storing a first plurality of memory pages and associated memory addresses, wherein the CPU receives a memory access request for a first memory address;
a watchpoint manager, connected to the CPU, for storing a watchpoint address list comprising a second plurality of memory pages and associated memory addresses, wherein for the watchpoint address list, a corresponding plurality of watchpoints are assigned by the front-end tool,
wherein the watchpoint manager receives the memory access request if the first-level DMI cache fails to complete the memory access request, searches the first memory address associated with the memory access request in the watchpoint address list, generates a watchpoint hit signal when the first memory address is present in the watchpoint address list, and notifies the front-end tool when the watchpoint hit signal is generated.
2. The functional simulator of claim 1 , wherein the CPU invalidates a DMI access to the first-level DMI cache corresponding to the second plurality of memory pages and associated memory addresses.
3. The functional simulator of claim 1 , wherein the watchpoint manager further includes a second-level DMI cache for storing a third plurality of memory pages and associated memory addresses of the second plurality of memory pages, and associated memory addresses that are present in the first-level DMI cache.
4. The functional simulator of claim 3 , wherein the watchpoint manager searches the first memory address in the second-level DMI cache when the first memory address is not present in the watchpoint address list.
5. The functional simulator of claim 4 , further comprising a memory controller, connected to the watchpoint manager, for receiving the memory access request from the watchpoint manager, and completing the memory access request when the first memory address is not present in the second-level DMI cache.
6. The functional simulator of claim 5 , further comprising an interconnect module, connected to the watchpoint manager and the memory controller, for simulating a bus system.
7. A method for operating a functional simulator with watchpoint support, wherein the functional simulator is run by a front-end tool, the functional simulator including a central processing unit (CPU) having a first-level direct memory interface (DMI) cache, a watchpoint manager having a second-level DMI cache, and a memory controller, the method comprising:
assigning a plurality of watchpoints to a first plurality of memory addresses by the front-end tool;
adding the plurality of watchpoints to a watchpoint address list by the watchpoint manager, wherein the watchpoint address list is stored in the second-level DMI cache;
invalidating a DMI access to the first-level DMI cache corresponding to a first plurality of memory pages associated with the first plurality of memory addresses, wherein the CPU invalidates the DMI access;
setting a plurality of access bits negative to prevent the DMI access to the first plurality of memory pages during execution of a subsequent memory access request, wherein the plurality of access bits is set by the CPU;
receiving a memory access request by the first-level DMI cache for a first memory address;
transmitting the memory access request to the watchpoint manager by the CPU if the first-level DMI caches fails to complete the memory access request;
searching for the first memory address associated with the memory access request in the watchpoint address list by the watchpoint manager;
generating a watchpoint hit signal when the first memory address is present in the watchpoint address list;
searching for the first memory address in the second-level DMI cache when the first memory address is not present in the watchpoint address list, wherein the second-level DMI cache stores a second plurality of memory pages and associated memory addresses of the first plurality of memory pages and associated memory addresses that are present in the first-level DMI cache; and
transmitting the memory access request to the memory controller for completing the memory access request when the first memory address is absent from the second-level DMI cache.
8. The method of claim 7 , further comprising the watchpoint manager notifying the front-end tool when the watchpoint hit signal is generated.
9. The method of claim 7 , wherein the memory access request is transmitted to the memory controller by way of an interconnect module, wherein the interconnect module simulates a bus system.