Granted Patent B2

US 9,665,377 · App. 14/125,200 · Granted May 30, 2017

Abstract

Claims (38)

1. A processing apparatus, comprising:

at least a first processing unit;

a second processing unit;

a set of synchronization data lines; and

a control unit;

said first processing unit comprising a set of first stateful elements;

said second processing unit comprising a set of second stateful elements;

said set of synchronization data lines being operable to connect said first stateful elements to said second stateful elements in a pairwise manner;

said control unit being operable to control said first processing unit, said second processing unit and said synchronization data lines so as to copy states of said first stateful elements in parallel via said synchronization data lines to said second stateful elements in response to a synchronization request.

2. The processing apparatus of claim 1 , each of said synchronization data lines comprising a multiplexer having:

an output connected to an input of one of said second stateful elements;

a normal data input; and

a synchronization data input connected to one of said second stateful elements.

3. The processing apparatus of claim 2 , said multiplexer being integrated in said second processing unit.

4. The processing apparatus of claim 2 , comprising a multiplexer control bus for feeding a multiplexer control signal to each of said multiplexers.

5. The processing apparatus of claim 4 , each of said multiplexers being arranged to connect said normal data input to said multiplexer output in response to said multiplexer control signal indicating a normal operating mode, and to connect said synchronization data input to said multiplexer output in response to said multiplexer control signal indicating a synchronization mode.

6. The processing apparatus of claim 5 , said control unit being arranged to control said multiplexer control signal to indicate said synchronization mode in response to said synchronization request, and to indicate said normal operating mode after completion of said copying.

7. The processing apparatus of claim 1 , comprising a scan chain, said scan chain comprising a subset of said second stateful elements.

8. The processing apparatus of claim 2 , comprising a scan chain, said scan chain comprising a subset of said second stateful elements and a subset of said multiplexers; each of said multiplexers of said scan chain having a scan data input connected to an output of a preceding stateful element of said scan chain.

9. The processing apparatus of claim 1 , said first processing unit being arranged to be clocked by a first clock signal, said second processing unit being arranged to be clocked by a second clock signal; said control unit being arranged to disable said first clock signal and said second clock signal in response to said synchronization request, and to enable said first clock signal and said second clock signal after completion of said copying.

10. The processing apparatus of claim 1 , said control unit being arranged to issue one or more clock pulses to said second processing unit so as to latch said states of said first stateful elements into said second stateful elements.

11. The processing apparatus of claim 10 , said control unit being arranged to issue said one or more clock pulses to said second processing unit but not to said first processing unit.

12. The processing apparatus of claim 1 , wherein said first and second stateful elements are single bit elements or multiple bit elements.

13. The processing apparatus of claim 1 , comprising a set of reverse synchronization data lines, said reverse synchronization data lines being operable to connect said second stateful elements to said first stateful elements in a pairwise manner;

said control unit being operable to control said first processing unit, said second processing unit and said reverse synchronization data lines so as to copy the states of said second stateful elements in parallel via said reverse synchronization data lines to said first stateful elements in response to a reverse synchronization request.

14. The processing apparatus of claim 3 , comprising a multiplexer control bus for feeding a multiplexer control signal to each of said multiplexers.

15. The processing apparatus of claim 2 , said first processing unit being arranged to be clocked by a first clock signal, said second processing unit being arranged to be clocked by a second clock signal; said control unit being arranged to disable said first clock signal and said second clock signal in response to said synchronization request, and to enable said first clock signal and said second clock signal after completion of said copying.

16. The processing apparatus of claim 2 , said control unit being arranged to issue one or more clock pulses to said second processing unit so as to latch said states of said first stateful elements into said second stateful elements.

17. The processing apparatus of claim 9 , said control unit being arranged to issue one or more clock pulses to said second processing unit so as to latch said states of said first stateful elements into said second stateful elements.

18. The processing apparatus of claim 7 , said control unit being arranged to issue one or more clock pulses to said second processing unit so as to latch said states of said first stateful elements into said second stateful elements.

19. A method of synchronizing a first processing unit and a second processing unit of a processing apparatus, said first processing unit comprising a set of first stateful elements, said second processing unit comprising a set of second stateful elements; said method comprising:

connecting said first stateful elements to said second stateful elements in a pairwise manner; and

copying states of said first stateful elements in parallel to said second stateful elements.

20. The method of claim 19 , comprising:

clocking said first processing unit and said second processing unit by a first clock signal and a second clock signal, respectively;

disabling said first clock signal and said second clock signal prior to said connecting;

issuing a clock pulse to said second stateful elements; and

enabling said first clock signal and said second clock signal.

Assignments (31)