Configurable flip-flop circuit
View Patent ↗A configurable flip-flop circuit has modifiable connections between its circuit elements that allow it to be modified for primary and secondary uses. For example, the flip-flop circuit can be modified to provide secondary functions of NOR and NAND gates during an implementation of an ECO. At other times, the flip-flop circuit can be used to deliver normal flip-flop functionality. A configurable latch circuit is provided that can be modified to provide an output signal or an inverted output signal. A scan circuit is provided that can provide the functionality of a multiplexer.
1. A flip-flop circuit ( 100 ) for effecting an Engineering Change Orders (ECO), wherein the flip-flop circuit generates an output signal based on an input signal and a clock signal, comprising:
a first transistor ( 106 ) having a source terminal for receiving a supply voltage, and a gate terminal for receiving the input signal;
a second transistor ( 108 ) having a source terminal connected to a drain terminal of the first transistor, and a gate terminal for receiving the clock signal;
a third transistor ( 110 ) having a drain terminal connected to a drain terminal of the second transistor, and a gate terminal for receiving an inverted version of the clock signal;
a fourth transistor ( 112 ) having a drain terminal connected to a source terminal of the third transistor, a gate terminal connected to the gate terminal of the first transistor, and a source terminal connected to ground;
a fifth transistor ( 114 ) having a source terminal for receiving the supply voltage;
a sixth transistor ( 116 ) having a source terminal connected to a drain terminal of the fifth transistor, and a gate terminal for receiving the inverted version of the clock signal;
a seventh transistor ( 118 ) having a drain terminal connected to a drain terminal of the sixth transistor, and a gate terminal for receiving the clock signal;
an eighth transistor ( 120 ) having a drain terminal connected to a source terminal of the seventh transistor, a source terminal connected to ground, and a gate terminal connected to a gate terminal of the fifth transistor, wherein to implement the flip-flop circuit, the drain terminals of the second and third transistors are connected to the drain terminals of the sixth and seventh transistors;
a NOR2A gate ( 102 ) for receiving a first intermediate input signal (I 1 ) and a reset signal, and generating the output signal, comprising:
a ninth transistor ( 142 ) having a source terminal for receiving the supply voltage, and a gate terminal for receiving an inverted version of the reset signal;
a tenth transistor ( 144 ) having a source terminal connected to a drain terminal of the ninth transistor, and a gate terminal for receiving the first intermediate input signal (I 1 );
an eleventh transistor ( 146 ) having a drain terminal connected to a drain terminal of the tenth transistor, a gate terminal connected to the gate terminal of the tenth transistor, and a source terminal shorted to ground, wherein a first intermediate output signal (O 1 ) is generated at the drain terminals of the tenth and eleventh transistors, and wherein to implement the flip-flop circuit the gate terminals of the tenth and eleventh transistors are connected to the drain terminals of the second and third transistors;
a twelfth transistor ( 148 ) having a drain terminal connected to the drain terminals of the tenth and eleventh transistors, a gate terminal connected to the gate terminal of the ninth transistor, and source terminal shorted to ground;
a thirteenth transistor ( 150 ) having a source terminal for receiving the supply voltage, and a gate terminal connected to the drain terminals of the tenth and eleventh transistors; and
a fourteenth transistor ( 152 ) having a drain terminal connected to a drain terminal of the thirteenth transistor, a gate terminal connected to the gate terminal of the thirteenth transistor, and a source terminal shorted to ground, wherein to implement the flip-flop circuit, the first intermediate output signal is applied to the gates of the fifth and eighth transistors;
a fifteenth transistor ( 122 ) having a gate terminal for receiving the inverted version of the clock signal;
a sixteenth transistor ( 124 ) having a gate terminal for receiving the clock signal, a drain terminal connected to a source terminal of the fifteenth transistor, and a source terminal connected to a drain terminal of the fifteenth transistor, wherein to implement the flip-flop circuit, the drain terminals of the thirteenth and fourteenth transistors are connected to the source terminal of the fifteenth transistor;
a seventeenth transistor ( 126 ) having a source terminal for receiving the supply voltage, and a gate terminal connected to the drain and source terminals of the fifteenth and sixteenth transistors, respectively; and
an eighteenth transistor ( 128 ) having a drain terminal connected to a drain terminal of the seventeenth transistor, a gate terminal connected to the gate terminal of the seventeenth transistor, and a source terminal shorted to ground, wherein a second intermediate input signal is generated at the drain terminals of the seventeenth and eighteenth transistors; and
a NAND gate ( 104 ) for receiving the second intermediate input signal (M 1 ) and the reset signal as a third intermediate input signal and generating a second intermediate output signal (E 1 ), comprising:
a nineteenth transistor ( 158 ) having a source terminal for receiving the supply voltage;
a twentieth transistor ( 160 ) having a source terminal connected to a drain terminal of the nineteenth transistor, and a gate terminal for receiving the clock signal;
a twenty-first transistor ( 162 ) having a drain terminal connected to a drain terminal of the twentieth transistor, and a gate terminal for receiving the inverted version of the clock signal;
a twenty-second transistor ( 164 ) having a drain terminal connected to a drain terminal of the twenty-first transistor, and a gate terminal connected to a gate terminal of the nineteenth transistor, wherein the second intermediate input signal (MI) is received at the gate terminals of the nineteenth and twenty-second transistors; and
a twenty-third transistor ( 166 ) having a drain terminal connected to a source terminal of the twenty-second transistor, a source terminal shorted to ground, and a gate terminal for receiving the reset signal; and
a twenty-fourth transistor ( 168 ) having a source terminal for receiving the supply voltage, a gate terminal for receiving the reset signal, and a drain terminal connected to the drain terminals of the twentieth and twenty-first transistors, wherein the second intermediate output signal (E 1 ) is generated at the drain terminal of the twenty-fourth transistor.
2. The flip-flop circuit of claim 1 , further comprising:
a twenty-fifth transistor ( 130 ) having a source terminal for receiving the supply voltage, and a gate terminal for receiving a clock source signal; and
a twenty-sixth transistor ( 132 ) having a drain terminal connected to a drain terminal of the twenty-fifth transistor, a gate terminal connected to the gate terminal of the twenty-fifth transistor, and a source terminal shorted to ground, wherein the inverted version of the clock signal is generated at the drain terminals of the twenty-fifth and twenty-sixth transistors.
3. The flip-flop circuit of claim 2 , further comprising:
a twenty-seventh transistor ( 134 ) having a source terminal for receiving the supply voltage, and a gate terminal for receiving the inverted version of the clock signal; and
a twenty-eighth transistor ( 136 ) having a drain terminal connected to a drain terminal of the twenty-seventh transistor, a gate terminal connected to the gate terminal of the twenty-seventh transistor, and a source terminal shorted to ground, wherein the clock signal is generated at the drain terminals of the twenty-seventh and twenty-eighth transistors.
4. The flip-flop circuit of claim 3 , wherein the NOR2A gate further includes:
a twenty-ninth transistor ( 138 ) having a source terminal for receiving the supply voltage, and a gate terminal for receiving the reset signal; and
a thirtieth transistor ( 140 ) having a drain terminal connected to a drain terminal of the twenty-ninth transistor, a gate terminal connected to the gate terminal of the twenty-ninth transistor, and a source terminal shorted to ground, wherein the inverted version of the reset signal is generated at the drain terminals of the twenty-ninth and thirtieth transistors.
5. The flip-flop circuit of claim 3 , wherein the NOR2A gate further includes:
a thirty-first transistor ( 154 ) having a source terminal for receiving the supply voltage, and wherein to implement the flip-flop circuit a gate terminal of the thirty-first transistor is connected to the drain terminal of twenty-fourth transistor for receiving the second intermediate output signal and for implementing the NOR2A gate, the drain terminals of the thirteenth and fourteenth transistors are connected to the gate terminal of the thirty-first transistor instead of to the source and drain terminals, respectively, of the fifteenth and sixteenth transistors; and
a thirty-second transistor ( 156 ) having a drain terminal connected to a drain terminal of the thirty-first transistor, a gate terminal connected to the gate terminal of the thirty-first transistor, and a source terminal shorted to ground, wherein the output signal (Q 1 ) is generated at the drain terminals of the thirty-first and thirty-second transistors.
6. The flip-flop circuit of claim 5 , wherein the first, second, fifth, sixth, ninth, tenth, thirteenth, fifteenth, seventeenth, nineteenth, twentieth, twenty-fourth, twenty-fifth, twenty-seventh, twenty-ninth, and thirty-first transistors are n-channel metal-oxide semiconductor (NMOS) transistors.
7. The flip-flop circuit of claim 5 , wherein the third, fourth, seventh, eighth, eleventh, twelfth, fourteenth, sixteenth, eighteenth, twenty-first, twenty-second, twenty-third, twenty-sixth, twenty-eighth, thirtieth, and thirty-second transistors are p-channel metal-oxide semiconductor (PMOS) transistors.
8. The flip-flop circuit of claim 5 , wherein the flip-flop circuit is of a positive-edge triggered D-type flip-flop with active low asynchronous reset.
9. A flip-flop circuit for effecting an Engineering Change Orders (ECO), wherein the flip-flop circuit generates an output signal based on an input signal and a clock signal, comprising:
a first transistor ( 206 ) having a source terminal for receiving a supply voltage, and a gate terminal for receiving the input signal;
a second transistor ( 208 ) having a source terminal connected to a drain terminal of the first transistor, and a gate terminal for receiving the clock signal;
a third transistor ( 210 ) having a drain terminal connected to a drain terminal of the second transistor, and a gate terminal for receiving an inverted version of the clock signal;
a fourth transistor ( 212 ) having a drain terminal connected to a source terminal of the third transistor, a gate terminal connected to the gate terminal of the first transistor, and a source terminal shorted to ground;
a fifth transistor ( 214 ) having a source terminal for receiving the supply voltage;
a sixth transistor ( 216 ) having a source terminal connected to a drain terminal of the fifth transistor, and a gate terminal for receiving the inverted version of the clock signal;
a seventh transistor ( 218 ) having a drain terminal connected to a drain terminal of the sixth transistor, and a gate terminal for receiving the clock signal;
an eighth transistor ( 220 ) having a drain terminal connected to a source terminal of the seventh transistor, a source terminal shorted to ground, and a gate terminal connected to a gate terminal of the fifth transistor, wherein to implement the flip-flop circuit, the drain terminals of the sixth and seventh transistors are connected to the drain terminals of the second and third transistors;
a NAND gate for receiving a set signal (SN) and a first intermediate input signal (I 2 ) and generating the output signal (Q 2 ), comprising:
a ninth transistor ( 238 ) having a source terminal for receiving the supply voltage, and a gate terminal for receiving the first intermediate input signal;
a tenth transistor ( 240 ) having a source terminal connected to a drain terminal of the ninth transistor, and a gate terminal connected to the gate terminal of the ninth transistor;
an eleventh transistor ( 242 ) having a drain terminal connected to a source terminal of the tenth transistor, a gate terminal for receiving e the set signal, and a source terminal shorted to ground;
a twelfth transistor ( 244 ) having a source terminal for receiving the supply voltage, a drain terminal connected to the drain terminals of the tenth and eleventh transistors, and a gate terminal for receiving the set signal;
a thirteenth transistor ( 246 ) having a source terminal for receiving the supply voltage, and a gate terminal connected to the drain terminals of the ninth and tenth transistors; and
a fourteenth transistor ( 248 ) having a drain terminal connected to a drain terminal of the thirteenth transistor, a gate terminal connected to the gate terminal of the thirteenth transistor, and a source
terminal shorted to ground, wherein to implement the flip-flop circuit, the gate terminals of the fifth and eighth transistors are connected to the gate terminals of the thirteenth and fourteenth transistors, and the gate terminals of the ninth and tenth transistors are connected to the drain terminals of the second and third transistors;
a fifteenth transistor ( 222 ) having a gate terminal for receiving the inverted version of the clock signal;
a sixteenth transistor ( 224 ) having a gate terminal for receiving the clock signal, a drain terminal connected to a source terminal of the fifteenth transistor, and a source terminal connected to a drain terminal of the fifteenth transistor, wherein to implement the flip-flop circuit, the drain terminals of the thirteenth and fourteenth transistors are connected to the source terminal of the fifteenth transistor;
a seventeenth transistor ( 226 ) having a source terminal for receiving the supply voltage, and a gate terminal connected to the drain and source terminals of the fifteenth and sixteenth transistors, respectively; and
an eighteenth transistor ( 228 ) having a drain terminal connected to a drain terminal of the seventeenth transistor, a gate terminal connected to the gate terminal of the seventeenth transistor, and a source terminal shorted to ground; and
a NOR2A gate ( 204 ) for receiving the set signal and a second intermediate signal (M 2 ), and generating a second intermediate output signal (E 2 ), comprising:
a nineteenth transistor ( 258 ) having a source terminal for receiving the supply voltage, and a gate terminal for receiving an inverted version of the set signal;
a twentieth transistor ( 260 ) having a source terminal connected to a drain terminal of the nineteenth transistor;
a twenty-first transistor ( 262 ) having a drain terminal connected to a drain terminal of the twentieth transistor, and a gate terminal for receiving the clock signal;
a twenty-second transistor ( 264 ) having a drain terminal connected to a source terminal of the twenty-first transistor, and a gate terminal for receiving the inverted version of the clock signal; and
a twenty-third transistor ( 266 ) having a drain terminal connected to a source terminal of the twenty-second transistor, a source terminal shorted to ground, and a gate terminal connected to the gate terminal of the twentieth transistor, and wherein to implement the NOR2A gate, the second intermediate input signal is applied to the gate terminals of the twenty and twenty-third transistors; and
a twenty-fourth transistor ( 268 ) having a drain terminal connected to the source and drain terminals of the twenty-first and twenty-second transistors, respectively, a gate terminal for receiving the inverted version of the set signal, and a source terminal shorted to ground, wherein the second intermediate output signal (E 2 ) is generated at the drain terminal of the twenty-fourth transistor.
10. The flip-flop circuit of claim 9 , further comprising:
a twenty-fifth transistor ( 230 ) having a source terminal for receiving the supply voltage, and a gate terminal for receiving a clock source signal; and
a twenty-sixth transistor ( 232 ) having a drain terminal connected to a drain terminal of the twenty-fifth transistor, a gate terminal connected to the gate terminal of the twenty-fifth transistor, and a source terminal shorted to ground, wherein the inverted version of the clock signal is generated at the drain terminals of the twenty-fifth and twenty-sixth transistors, wherein to implement the flip-flop circuit, the gate terminals of the twenty and twenty-third transistors are connected to the drain terminals of the seventeenth and eighteenth transistors.
11. The flip-flop circuit of claim 10 , further comprising:
a twenty-seventh transistor ( 234 ) having a source terminal for receiving the supply voltage, and a gate terminal for receiving the inverted version of the clock signal from the drain terminals of the twenty-fifth and twenty-sixth transistors; and
a twenty-eighth transistor ( 236 ) having a drain terminal connected to a drain terminal of the twenty-seventh transistor, a gate terminal connected to the gate terminal of the twenty-seventh transistor, and a source terminal shorted to ground, wherein the clock signal is generated at the drain terminals of the twenty-seventh and twenty-eighth transistors.
12. The flip-flop circuit of claim 11 , wherein the NOR2A gate further includes:
a twenty-ninth transistor ( 254 ) having a source terminal for receiving the supply voltage, and a gate terminal for receiving the set signal; and
a thirtieth transistor ( 256 ) having a drain terminal connected to a drain terminal of the twenty-ninth transistor, a gate terminal connected to the gate terminal of the twenty-ninth transistor, and a source terminal shorted to ground, wherein the inverted version of the set signal is generated at the drain terminals of the twenty-ninth and thirtieth transistors.
13. The flip-flop circuit of claim 12 , wherein the NAND gate further includes:
a thirty-first transistor ( 250 ) having a source terminal for receiving the supply voltage; and
a thirty-second transistor ( 252 ) having a drain terminal connected to a drain terminal of the thirty-first transistor, a gate terminal connected to a gate terminal of the thirty-first transistor, and a source terminal shorted to ground, wherein to implement the flip-flop circuit, the gate terminals of the thirty-first and thirty-second transistors are connected to the drain terminal of the twenty-fourth transistor, and wherein the output signal is generated at the drain terminals of the thirty-first and thirty-second transistors, and wherein to implement the NAND gate, the gate terminals of the thirty-first and thirty-second transistors are connected to the drain terminals of the thirteenth and fourteenth transistors instead of to the source terminal of the twenty-fourth transistor, and instead of to the source and drain terminals of the fifteenth and sixteenth transistors, respectively.
14. The flip-flop circuit of claim 13 , wherein the first, second, fifth, sixth, ninth, twelfth, thirteenth, fifteenth, seventeenth, nineteenth, twentieth, twenty-fifth, twenty-seventh, twenty-ninth, and thirty-first transistors are n-channel metal-oxide semiconductor (NMOS) transistors.
15. The flip-flop circuit of claim 14 , wherein the third, fourth, seventh, eighth, tenth, eleventh, fourteenth, sixteenth, eighteenth, twenty-first, twenty-second, twenty-third, twenty-fourth, twenty-sixth, twenty-eighth, thirtieth, and thirty-second transistors are p-channel metal-oxide semiconductor (PMOS) transistors.
16. The flip-flop circuit of claim 13 , wherein the flip-flop circuit is of a positive-edge triggered D-type flip-flop with active low asynchronous set.