IP Library Granted Patent US 9,099,567
Granted Patent B2
US 9,099,567 · App. 14/089,744 · Granted Aug 4, 2015

Packaged semiconductor devices and methods of their fabrication

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Quick Facts
Patent No.
US 9,099,567
App. No.
14/089,744
Granted
Aug 4, 2015
Kind
B2
Abstract

An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.

Claims (36)

1. A method of attaching a semiconductor die to a substrate, the method comprising:

placing a bottom surface of a semiconductor die over a top surface of a substrate with a die attach material between the bottom surface of the semiconductor die and the top surface of the substrate, resulting in an assembly that includes the substrate, the die attach material, and the semiconductor die;

contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material;

applying a pressure to the conformal structure, wherein the pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die; and

while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.

2. The method of claim 1 , wherein the conformal structure includes a conformal solid and the non-solid, pressure transmissive material, wherein during the contacting step, the conformal solid directly contacts the top surfaces of the semiconductor die and the substrate, and the non-solid, pressure transmissive material is physically separated from the top surfaces of the semiconductor die and the substrate by the conformal solid.

3. The method of claim 2 , wherein contacting the top surface of the semiconductor die with the conformal structure comprises:

applying the conformal solid over the top surface of the substrate and the top surface of the semiconductor die, wherein the conformal solid is selected from a conformal film, a foil, and a solid material layer; and

exposing the conformal solid to the non-solid, pressure transmissive material.

4. The method of claim 3 , wherein exposing the conformal solid to the non-solid, pressure transmissive material is selected from depositing the non-solid, pressure transmissive material over the conformal solid, and inserting the assembly with the conformal solid into a vessel that includes the non-solid, pressure transmissive material.

5. The method of claim 2 , wherein the conformal solid comprises a container suitable for containing the non-solid, pressure transmissive material, wherein the container is selected from a balloon having a size that may vary in response to pressure asserted on an inside of the balloon by the non-solid, pressure transmissive material, and a bag having a size that does not significantly vary in response to pressure asserted on an inside of the bag by the non-solid, pressure transmissive material.

6. The method of claim 2 , wherein the conformal solid comprises a material that remains solid when exposed to the temperature that is sufficient to cause the die attach material to sinter.

7. The method of claim 1 , further comprising:

applying the die attach material to the bottom surface of the semiconductor die, the top surface of the substrate, or both the bottom surface of the semiconductor die and the top surface of the substrate, and wherein applying the die attach material comprises applying a die attach material that includes metallic particles configured to produce a sintered metal when exposed to a temperature sufficient for sintering to occur.

8. The method of claim 7 , wherein the metallic particles are selected from silver particles, gold particles, copper particles, nickel particles, and palladium particles.

9. The method of claim 7 , wherein the metallic particles have sizes in a range of 10 nanometers to 100 nanometers.

10. The method of claim 1 , further comprising:

before placing the bottom surface of the semiconductor die over the top surface of the substrate, forming a plurality of first conductive mechanical lock features on the top surface of the substrate, and forming a plurality of second conductive mechanical lock features on the bottom surface of the semiconductor die.

11. The method of claim 10 , wherein the first and second conductive mechanical lock features are formed using a technique selected from selective chemical etching, sputter etching, and selective plating.

12. The method of claim 1 , wherein the non-solid, pressure transmissive material is selected from a gas, a liquid, a paste, a putty, and a gel.

13. The method of claim 1 , wherein applying the pressure to the conformal structure is selected from applying mechanical pressure, applying hydraulic pressure, and applying pneumatic pressure.

14. The method of claim 1 , wherein applying the pressure comprises applying a pressure in a range of 3.0 megapascals to 30.0 megapascals.

15. The method of claim 1 , wherein exposing the assembly to the temperature comprises exposing the assembly to a temperature in a range of 200 degrees Celsius to 800 degrees Celsius.

16. The method of claim 1 , wherein the die attach material includes an additive material configured to increase a thermal conductivity of the die attach material during operation of a device that includes the assembly.

17. The method of claim 16 , wherein the additive material is selected from graphene, diamond particles, silicon carbide, titanium carbide, and boron nitride.

18. The method of claim 1 , further comprising exposing the die attach material to ultrasonic energy while exposing the assembly to the temperature.

19. The method of claim 1 , wherein exposing the assembly to the temperature is selected from exposing the assembly to an elevated temperature within an oven, exposing the assembly to microwave radiation, and a combination thereof.

20. The method of claim 1 , wherein the substrate forms a portion of a structure that includes multiple interconnected substrates, and wherein the steps of placing, contacting, applying, and exposing are performed in parallel with some or all of the interconnected substrates in order to attach multiple semiconductor die to the multiple interconnected substrates in parallel.

21. A method of attaching a semiconductor die to a substrate, the method comprising:

placing a bottom surface of a semiconductor die over a top surface of a substrate with a die attach material that contains silver particles between the bottom surface of the semiconductor die and the top surface of the substrate, resulting in an assembly that includes the substrate, the die attach material, and the semiconductor die;

contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure, wherein the conformal structure includes a conformal solid that directly contacts the top surfaces of the semiconductor die and the substrate, and a non-solid, pressure transmissive material that is physically separated from the top surfaces of the semiconductor die and the substrate by the conformal solid; applying a pressure to the conformal structure, wherein the pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die; and

while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the silver particles to sinter.

22. The method of claim 21 , wherein the silver particles have sizes in a range of 10 nanometers to 100 nanometers.

23. The method of claim 21 , wherein the non-solid, pressure transmissive material is selected from a gas, a liquid, a paste, a putty, and a gel.

24. The method of claim 21 , wherein applying the pressure to the conformal structure is selected from applying mechanical pressure, applying hydraulic pressure, and applying pneumatic pressure.

25. The method of claim 21 , wherein exposing the assembly to the temperature comprises exposing the assembly to a temperature in a range of 200 degrees Celsius to 800 degrees Celsius.

Assignments (22)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039138/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FILING AND REMOVE APPL. NO. 14085520 REPLACE IT WITH 14086520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Mar 1, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037926/0642 →
CORRECTIVE ASSIGNMENT OF INCORRECT PATENT APPLICATION NUMBER 14085520 ,PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0399. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037785/0454 →
CORRECTIVE ASSIGNMENT OF INCORRECT NUMBER 14085520 PREVIOUSLY RECORDED AT REEL: 037458 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTON OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037785/0568 →
CORRECTIVE ASSIGNMENT OF INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0390. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037792/0227 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT APPL. NO. 14/085,520 PREVIOUSLY RECORDED AT REEL: 037515 FRAME: 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 11, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037879/0581 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 037458 FRAME 0420. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Jan 14, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037515/0420 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 037458 FRAME 0399. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Jan 14, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037515/0390 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FOUNDING, INC.
Reel/Frame 037458/0420 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 7, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FOUNDING, INC.
Reel/Frame 037458/0399 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0790 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032445/0493 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 032445/0577 →
SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 13, 2014
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., COLLATERAL AGENT
Reel/Frame 032445/0689 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2014
From: VISWANATHAN, LAKSHMINARAYAN; MAHALINGAM, L. M.; ABDO, DAVID F.; MOLLA, JAYNAL A.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 031975/0653 →