Semiconductor device with relaxation reduction liner and associated methods

1. A method for forming a semiconductor device comprising:

forming a mask layer on a stressed semiconductor layer of a stressed semiconductor-on-insulator (SOI) wafer comprising a substrate, an oxide layer on the substrate, and the stressed semiconductor layer on the oxide layer, the oxide layer having a substantially uniform thickness;

forming an isolation trench through the stressed semiconductor layer, through the mask layer, and into the substrate, the isolation trench exposing first and second side surfaces of the stressed semiconductor layer within the isolation trench, the first and second side surfaces of the stressed semiconductor layer facing each other;

forming a dielectric body in the isolation trench, the dielectric body directly contacting the oxide layer and the substrate, the dielectric body extending between the first and second side surfaces of the stressed semiconductor layer;

forming a relaxation reduction liner on the dielectric body extending between and abutting the first and second side surfaces of the stressed semiconductor layer within the isolation trench, a portion of the relaxation reduction liner being on the mask layer;

removing the mask layer and the portion of the relaxation reduction liner on the mask layer from the stressed semiconductor layer, a first upper surface of the relaxation reduction liner being substantially coplanar with an upper surface of the stressed semiconductor layer after removing the mask layer;

forming at least one of a source region and a drain region in the stressed semiconductor layer, the stressed semiconductor layer and the at least one of a source region and a drain region having a same thickness, the at least one of a source region and a drain region overlying and in direct contact with the oxide layer and abutting the relaxation reduction liner; and

forming a gate stack over the stressed semiconductor layer after removing the mask layer and the portion of the relaxation reduction liner.

2. The method according to claim 1 wherein the relaxation reduction liner comprises aluminum oxide.

3. The method according to claim 1 wherein the relaxation reduction liner comprises hafnium oxide.

4. The method according to claim 1 wherein the relaxation reduction liner has a Young's modulus greater than 70 GPa.

5. The method according to claim 1 wherein the stressed semiconductor layer comprises silicon.

6. The method according to claim 1 wherein the stressed semiconductor layer comprises silicon and germanium.

7. The method according to claim 1 wherein a second upper surface of the relaxation reduction liner is abutting the first side surface of the stressed semiconductor layer and is formed to be above the upper surface of the stressed semiconductor layer.

8. The method according to claim 1 wherein forming the at least one of a source region and a drain region includes forming raised source and drain regions defining a channel therebetween under the gate stack.

9. The method according to claim 8 wherein the channel is for a metal-oxide semiconductor field-effect transistor (MOSFET) having a FinFET structure.

10. A method for forming a semiconductor device comprising:

forming a mask layer on a stressed silicon layer of a stressed silicon-on-insulator (SOI) wafer comprising a substrate, an oxide layer on the substrate, and the stressed silicon layer on the oxide layer;

forming an isolation trench through the stressed silicon layer, through the mask layer, and into the substrate, the isolation trench exposing first and second side surfaces of the stressed silicon layer within the isolation trench;

forming a dielectric body in the isolation trench, the dielectric body directly contacting the oxide layer and the substrate;

forming a liner including at least one of aluminum oxide and hafnium oxide on the dielectric body extending between and abutting the first and second side surfaces of the stressed silicon layer within the isolation trench, a portion of the liner being on the mask layer;

removing the mask layer and the portion of the liner on the mask layer from the stressed silicon layer, a first upper surface of the liner being substantially coplanar with an upper surface of the stressed silicon layer after removing the mask layer;

forming at least one of a source region and a drain region in the stressed silicon layer, the stressed silicon layer and the at least one of a source region and a drain region having a same thickness, the at least one of a source region and a drain region overlying and in direct contact with the oxide layer and in direct contact with the liner; and

forming a gate stack over the stressed silicon layer after removing the mask layer and the portion of the liner.

11. The method according to claim 10 wherein the stressed silicon layer comprises silicon and germanium.

12. The method according to claim 10 wherein a second upper surface of the liner on the adjacent sidewall of the stressed silicon layer is formed to be above the upper surface of the stressed silicon layer.

13. The method according to claim 10 wherein forming the at least one of a source region and a drain region includes forming raised source and drain regions defining a channel therebetween under the gate stack.

14. The method according to claim 13 wherein the channel is for a metal-oxide semiconductor field-effect transistor (MOSFET) having a FinFET structure.

15. A semiconductor device comprising:

a stressed semiconductor-on-insulator (SOI) substrate comprising a substrate, an oxide layer on said substrate, and a stressed semiconductor layer on said oxide layer, the oxide layer having a substantially uniform thickness;

a shallow trench isolation (STI) adjacent to said stressed semiconductor layer in said SOI substrate, with said STI extending into said SOI substrate past said oxide layer, with said STI directly contacting said oxide layer and said substrate;

a relaxation reduction liner on said STI and extending between and abutting first and second side surfaces of said stressed semiconductor layer, a first upper surface of the relaxation reduction liner being substantially coplanar with an upper surface of the stressed semiconductor layer;

source and drain regions formed in the stressed semiconductor layer, each of the source and drain regions overlying and in direct contact with the oxide layer and in abutting contact with side surfaces of the relaxation reduction liner; and

a gate stack on the stressed semiconductor layer, the gate stack overlying portions of the source and drain regions.

16. The semiconductor device according to claim 15 wherein said relaxation reduction liner comprises aluminum oxide.

17. The semiconductor device according to claim 15 wherein said relaxation reduction liner comprises hafnium oxide.

18. The semiconductor device according to claim 15 wherein said relaxation reduction liner has a Young's modulus greater than 70 GPa.

19. The semiconductor device according to claim 15 wherein said stressed semiconductor layer comprises silicon.

20. The semiconductor device according to claim 15 wherein said stressed semiconductor layer comprises silicon and germanium.

21. The semiconductor device according to claim 15 wherein a second upper surface of said relaxation reduction liner abutting the first side surface of said stressed semiconductor layer is above the upper surface of said stressed semiconductor layer.

22. The semiconductor device according to claim 15 wherein the source and drain regions include raised source and drain regions defining a channel therebetween under said gate stack.

23. The semiconductor device according to claim 22 wherein the channel is for a metal-oxide semiconductor field-effect transistor (MOSFET) having a FinFET structure.