Approach to caching decoded texture data with variable dimensions
A texture processing pipeline is configured to store decoded texture data within a cache unit in order to expedite the processing of texture requests. When a texture request is processed, the texture processing pipeline queries the cache unit to determine whether the requested data is resident in the cache. If the data is not resident in the cache unit, a cache miss occurs. The texture processing pipeline then reads encoded texture data from global memory, decodes that data, and writes different portions of the decoded memory into the cache unit at specific locations according to a caching map. If the data is, in fact, resident in the cache unit, a cache hit occurs, and the texture processing pipeline then reads decoded portions of the requested texture data from the cache unit and combines those portions according to the caching map.
1. A computer-implemented method for caching data being processed in a texture processing pipeline, the method comprising:
receiving a memory access request indicating that a data block should be returned from memory;
determining that the data block does not reside in a cache unit associated with the texture processing pipeline, wherein the cache unit comprises a plurality of sectors, each sector comprising a plurality of banks;
retrieving an encoded version of the data block from a global memory;
decoding the encoded version of the data block to produce the data block comprising a height dimension and a width dimension in texels, wherein a data block comprises a texture comprising a plurality of regions, each region comprising a plurality of texels;
retrieving a first caching map from a plurality of caching maps based on the height and width dimensions of the data block, wherein the first caching map specifies that adjacent regions of the data block are stored in different sectors of the cache unit and adjacent texels of the data block are stored in different banks of the cache unit; and
storing a first texel of the data block at a particular location within the cache unit according to the first caching map.
2. The computer-implemented method of claim 1 , wherein storing the first texel of the data block comprises:
identifying a first cache line within the cache unit that is available to store the first texel of the data block;
identifying a first cell included in the first caching map that corresponds to the first texel of the data block, wherein the first caching map includes a different cell for each portion of the data block;
determining a sector within the first cache line based on the first cell;
determining a bank associated with the sector based on the first cell; and
storing the first texel of data within the bank.
3. The computer-implemented method of claim 2 , wherein identifying the first cache line within the cache unit comprises;
determining a set of cache lines within which the first texel of the data block should be stored according to the first caching map, wherein the first cache line is included in the set of cache lines; and
identifying the first cache line as being available to store the first texel of the data block.
4. The computer-implemented method of claim 1 , further comprising transmitting the data block to a processing engine to fulfill the memory access request.
5. The computer-implemented method of claim 1 , further comprising:
receiving another memory access request indicating that the data block should be returned from memory;
determining that the data block resides in the cache unit;
retrieving each portion of the data block from a different location within the cache unit according to the first caching map; and
combining the portions of the data block to reconstruct the data block.
6. The computer-implemented method of claim 5 , further comprising transmitting the data block to a processing engine to fulfill the memory access request.
7. The computer-implemented method of claim 1 , wherein the data block is encoded according to an advanced scalable texture compression (ASTC) encoding standard to produce the encoded version of the data block.
8. The computer-implemented method of claim 1 , wherein the data block comprises a plurality of different portions, and the first caching map specifies, for each of the different portions, a location where the different portion is to be stored within the cache unit.
9. The computer-implemented method of claim 1 , wherein each caching map in the plurality of caching maps corresponds to a particular set of data block dimensions.
10. A subsystem configured to cache data being processed in a texture processing pipeline, including:
the processing pipeline, configured to:
receive a memory access request indicating that a data block should be returned from memory;
determine that the data block does not reside in a cache unit associated with the texture processing pipeline, wherein the cache unit comprises a plurality of sectors, each sector comprising a plurality of banks;
retrieve an encoded version of the data block from a global memory;
decode the encoded version of the data block to produce the data block comprising a height dimension and a width dimension in texels, wherein a data block comprises a texture comprising a plurality of regions, each region comprising a plurality of texels;
retrieve a first caching map from a plurality of caching maps based on the height and width dimensions of the data block, wherein the first caching map specifies that adjacent regions of the data block are stored in different sectors of the cache unit and adjacent texels of the data block are stored in different banks of the cache unit; and
store a first texel of the data block at a particular location within the cache unit according to the first caching map.
11. The subsystem of claim 10 , wherein the processing pipeline is configured to store the first texel of the data block by:
identifying a first cache line within the cache unit that is available to store the first texel of the data block;
identifying a first cell included in the first caching map that corresponds to the first texel of the data block, wherein the first caching map includes a different cell for each portion of the data block;
determining a sector within the first cache line based on the first cell;
determining a bank associated with the sector based on the first cell; and
storing the first texel of data within the bank.
12. The subsystem of claim 11 , wherein the processing pipeline is configured to identify the first cache line within the cache unit by:
determining a set of cache lines within which the first texel of the data block should be stored according to the first caching map, wherein the first cache line is included in the set of cache lines; and
identifying the first cache line as being available to store the first texel of the data block.
13. The subsystem of claim 10 , wherein the processing pipeline is further configured to transmit the data block to a processing engine to fulfill the memory access request.
14. The subsystem of claim 10 , wherein the processing pipeline is further configured to:
receive another memory access request indicating that the data block should be returned from memory;
determine that the data block resides in the cache unit;
retrieve each portion of the data block from a different location within the cache unit according to the first caching map; and
combine the portions of the data block to reconstruct the data block.
15. The subsystem of claim 14 , wherein the processing pipeline is further configured to transmit the data block to a processing engine to fulfill the memory access request.
16. The subsystem of claim 10 , wherein the data block is encoded according to an advanced scalable texture compression (ASTC) encoding standard to produce the encoded version of the data block.
17. The subsystem of claim 10 , wherein the width dimension comprises a first number of texels and the height dimension comprises a second number of texels.
18. The subsystem of claim 10 , wherein the processing pipeline is configured to retrieve the first caching map from a memory that stores a plurality of caching maps, and each caching map included in the plurality of caching maps is associated with a different set of data block dimensions.
19. A computing device configured to cache data being processed in a processing pipeline, including:
the processing pipeline, configured to:
receive a memory access request indicating that a data block should be returned from memory;
determine that the data block does not reside in a cache unit associated with the texture processing pipeline, wherein the cache unit comprises a plurality of sectors, each sector comprising a plurality of banks;
retrieve an encoded version of the data block from a global memory;
decode the encoded version of the data block to produce the data block comprising a height dimension and a width dimension in texels, wherein a data block comprises a texture comprising a plurality of regions, each region comprising a plurality of texels;
retrieve a first caching map from a plurality of caching maps based on the height and width dimensions of the data block, wherein the first caching map specifies that adjacent regions of the data block are stored in different sectors of the cache unit and adjacent texels of the data block are stored in different banks of the cache unit; and
store a first texel of the data block at a particular location within the cache unit according to the first caching map.
20. The computing device of claim 19 , wherein the processing pipeline is configured to store the first texel of the data block by:
identifying a first cache line within the cache unit that is available to store the first texel of the data block;
identifying a first cell included in the first caching map that corresponds to the first texel of the data block, wherein the first caching map includes a different cell for each portion of the data block;
determining a sector within the first cache line based on the first cell;
determining a bank associated with the sector based on the first cell; and
storing the first texel of data within the bank.
21. The computing device of claim 20 , wherein the processing pipeline is configured to identify the first cache line within the cache unit by:
determining a set of cache lines within which the first texel of the data block should be stored according to the first caching map, wherein the first cache line is included in the set of cache lines; and
identifying the first cache line as being available to store the first texel of the data block.
22. The computing device of claim 19 , wherein the processing pipeline is further configured to transmit the data block to a processing engine to fulfill the memory access request.