IP Library Granted Patent US 8,897,051
Granted Patent B2
US 8,897,051 · App. 14/052,864 · Granted Nov 25, 2014

Semiconductor storage device and method for producing the same

Inventors: Satoru Itakura (Kawasaki, JP); Akio Katsumata (Kawasaki, JP); Akihiro Umeki (Kawasaki, JP); Yasushi Shiraishi (Kawasaki, JP); Junichiro Abe (Kawasaki, JP)
Assignee: J-Devices Corporation
G11C16/30G11C11/4096G11C5/06G11C5/02G11C5/063G11C5/025G11C7/10G11C7/1069G06F3/00H01L25/0657H01L25/105H01L25/18H01L22/10H01L2224/16225H01L2924/15311H01L2924/19105
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Quick Facts
Patent No.
US 8,897,051
App. No.
14/052,864
Granted
Nov 25, 2014
Kind
B2
Abstract

A semiconductor storage device 100 includes a controller package 110 having a BGA terminal on a bottom surface thereof; and one or a plurality of memory packages 120 each including a plurality of semiconductor storage elements and mounted on the controller package. The controller package includes a bottom substrate having the BGA terminal on a bottom surface thereof; a power supply IC, mounted on the bottom substrate, for supplying a plurality of power supplies; and a controller mounted on the bottom substrate and operable by the plurality of power supplies supplied from the power supply IC. The controller provides an interface with an external system via the BGA terminal and controls a read operation from the semiconductor storage elements and a write operation to the semiconductor storage elements.

Claims (32)

1. A semiconductor storage device, comprising:

a controller package having a BGA terminal on a bottom surface thereof; and

one or a plurality of memory packages each including a plurality of semiconductor storage elements and mounted on the controller package;

wherein:

(A) the controller package includes:

a bottom substrate having the BGA terminal on a bottom surface thereof;

a power supply IC, mounted on the bottom substrate, for supplying a plurality of power supplies; and

a controller mounted on the bottom substrate and operable by the plurality of power supplies supplied from the power supply IC, the controller providing an interface with an external system via the BGA terminal and controlling a read operation from the semiconductor storage elements and a write operation to the semiconductor storage elements;

wherein a memory terminal pattern for mounting the one or plurality of memory packages thereon is formed on a top surface of the controller package, the memory terminal pattern being connected to the controller; and

(B) the one or plurality of memory packages are mounted on, and electrically connected to, the memory terminal pattern.

2. A semiconductor storage device according to claim 1 , wherein the controller includes:

an external interface interfacing with the external system; and

a core unit for controlling the read operation and the write operation;

wherein the external interface unit is supplied with a first power supply voltage from the power supply IC, and the core unit is supplied with a second power supply voltage from the power supply IC.

3. A semiconductor storage device according to claim 2 , wherein:

the controller further includes a memory interface unit for interfacing with the semiconductor storage elements;

the semiconductor storage elements each include a controller interface unit for interfacing with the controller and a memory core unit for storing information; and

the memory interface unit and the controller interface unit are each supplied with a third power supply voltage from the power supply IC.

4. A semiconductor storage device according to claim 1 , wherein:

the BGA terminal includes a plurality of terminals located in a prescribed pattern;

a part of the plurality of terminals is used for interfacing with the external system or for supplying a power supply; and

another part of the plurality of terminals includes dummy terminals which are not used for interfacing or providing a power supply.

5. A method for producing a semiconductor storage device, comprising:

providing the semiconductor storage device including:

a controller package having a BGA terminal on a bottom surface thereof; and

one or a plurality of memory packages each including a plurality of semiconductor storage elements and mounted on the controller package;

wherein the controller package includes:

a bottom substrate having the BGA terminal on a bottom surface thereof;

a power supply IC, mounted on the bottom substrate, for supplying a plurality of power supplies; and

a controller mounted on the bottom substrate and operable by the plurality of power supplies supplied from the power supply IC, the controller providing an interface with an external system via the BGA terminal and controlling a read operation from the semiconductor storage elements and a write operation to the semiconductor storage elements;

wherein a memory terminal pattern for mounting the one or plurality of memory packages thereon is formed on a top surface of the controller package, the memory terminal pattern being connected to the controller; and

stacking and connecting the controller package selected as being good by a first test and the one or plurality of memory packages selected as being good by a second test.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYING PARTY NAME PREVIOUSLY RECORDED AT REEL: 53597 FRAME: 184. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 5, 2021
From: J-DEVICES CORPORATION
To: AMKOR TECHNOLOGY JAPAN, INC.
Reel/Frame 055605/0060 →
CHANGE OF NAME Recorded Aug 25, 2020
From: J-DEVICES CO., LTD.
To: AMKOR TECHNOLOGY JAPAN, INC.
Reel/Frame 053597/0184 →
RECORD TO CORRECT THE THIRD ASSIGNOR'S NAME TO AKIHIRO UMEKI, PREVIOUSLY RECORDED AT REEL 031656, FRAME 0499. Recorded Dec 11, 2013
From: ITAKURA, SATORU; KATSUMATA, AKIO; UMEKI, AKIHIRO; SHIRAISHI, YASUSHI; ABE, JUNICHIRO
To: J-DEVICES CORPORATION
Reel/Frame 032057/0192 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 1, 2013
From: ITAKURA, SATORU; KATSUMATA, AKIO; UMEKI, AKHIRO; SHIRAISHI, YASUSHI; ABE, JUNICHIRO
To: J-DEVICES CORPORATION
Reel/Frame 031656/0499 →
Priority Claims (1)
JP 2012-227643 · Oct 15, 2012 · national
Continuity (1)
Related Publication 20140104953A1 · Apr 17, 2014