Nanowire MOSFET with support structures for source and drain
A transistor device and method for forming a nanowire field effect transistor (FET) device are provided. A device layer including a source region and a drain region is formed, where the source region and the drain region are connected by a suspended nanowire channel. Etch stop layers are formed beneath the source region and the drain region. The etch stop layers comprise support structures interposed between a semiconductor substrate and the source and drain regions. The suspended nanowire channel is formed by etching a sacrificial material beneath the suspended nanowire channel. The etching is selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region.
1. A method for forming a nanowire field effect transistor (FET) device, the method comprising:
forming a device layer including a source region and a drain region, the source region and the drain region being connected by a nanowire channel to be suspended
the nanowire channel being provided over a sacrificial material;
forming etch stop layers beneath the source region and the drain region, the etch stop layers comprising support structures interposed between a semiconductor substrate and the source and drain regions,
the etch stop layers selectively including at least one of a carbon-doped silicon layer, a non-doped silicon layer, and a boron-doped silicon layer; and
suspending the nanowire channel by:
etching the sacrificial material beneath the nanowire channel, the etching being selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region.
2. The method of claim 1 , further comprising:
forming the etch stop layers, wherein the etch stop layers include the carbon-doped silicon layer; and
etching the sacrificial material, wherein the sacrificial material includes SiGe.
3. The method of claim 2 , further comprising:
forming the carbon-doped silicon layer using an epitaxial process.
4. The method of claim 2 , further comprising:
forming a well of a first conductivity type in the semiconductor substrate; and
forming the carbon-doped silicon layer, wherein a resistivity characteristic of the carbon-doped silicon layer causes the carbon-doped silicon layer to electrically isolate the source region, the drain region, or the suspended nanowire channel from the well.
5. The method of claim 2 , further comprising:
forming a well of a first conductivity type in the semiconductor substrate;
forming an anti-punch-through layer of the first conductivity type in the well via an implantation process; and
forming the carbon-doped silicon layer, wherein the carbon-doped silicon layer is i) adjacent to the source region or the drain region, and ii) adjacent to the anti-punch-through layer.
6. The method of claim 5 , wherein the first conductivity type is p-type.
7. The method of claim 5 , wherein the first conductivity type is n-type.
8. The method of claim 2 , further comprising:
forming the source region, wherein the source region includes SiP;
forming the drain region, wherein the drain region includes SiP; and
forming the carbon-doped silicon layer, wherein the carbon-doped silicon layer is adjacent to the source region or the drain region, and wherein the carbon-doped silicon layer decreases diffusion of SiP to portions of the FET device.
9. The method of claim 8 , further comprising:
subjecting the device layer and the etch stop layers to a high temperature process, wherein the carbon-doped silicon layer decreases the diffusion of the SiP during the high temperature process.
10. The method of claim 2 , further comprising:
forming the etch stop layers, wherein the etch stop layers include:
the non-doped silicon layer, and
the carbon-doped silicon layer that is i) adjacent to the source region or the drain region, and ii) stacked vertically over the non-doped silicon layer.
11. The method of claim 10 , further comprising:
forming the non-doped silicon layer, wherein the non-doped silicon layer is adjacent to the semiconductor substrate.
12. The method of claim 10 , further comprising:
forming the source region, wherein the source region includes SiP;
forming the drain region, wherein the drain region includes SiP; and
forming the carbon-doped silicon layer, wherein the carbon-doped silicon layer decreases diffusion of SiP to the non-doped silicon layer and to the semiconductor substrate.
13. The method of claim 10 , further comprising:
forming the etch stop layers, wherein a thickness of the non-doped silicon layer is greater than a thickness of the carbon-doped silicon layer.
14. The method of claim 10 , further comprising:
forming a well of a first conductivity type in the semiconductor substrate;
forming an anti-punch-through layer of the first conductivity type in the well via an implantation process; and
forming the non-doped silicon layer, wherein the non-doped silicon layer is adjacent to the anti-punch-through layer.
15. The method of claim 2 , further comprising:
forming the etch stop layers, wherein the etch stop layers include:
the boron-doped silicon layer, and
the carbon-doped silicon layer that is i) adjacent to the source region or the drain region, and ii) stacked vertically over the boron-doped silicon layer.
16. The method of claim 15 , further comprising:
forming the boron-doped silicon layer, wherein the boron-doped silicon layer is adjacent to the semiconductor substrate.
17. The method of claim 15 , further comprising:
forming the boron-doped silicon layer using a first epitaxial process; and
forming the carbon-doped silicon layer using a second epitaxial process.
18. The method of claim 15 , further comprising:
forming the source region, wherein the source region includes SiP;
forming the drain region, wherein the drain region includes SiP; and
forming the carbon-doped silicon layer, wherein the carbon-doped silicon layer decreases diffusion of SiP to the boron-doped silicon layer.
19. The method of claim 15 , further comprising:
forming the etch stop layers, wherein a thickness of the boron-doped silicon layer is less than a thickness of the carbon-doped silicon layer.
20. The method of claim 15 , further comprising:
forming a well of a first conductivity type in the semiconductor substrate; and
forming the boron-doped silicon layer via an epitaxial process, wherein the boron-doped silicon layer serves as an anti-punch-through layer, and wherein the FET device does not include an anti-punch-through layer formed via an implantation process.
21. A transistor device comprising:
a semiconductor substrate;
a device layer including a source region and a drain region, the source region and the drain region being connected by a suspended nanowire channel; and
etch stop layers respectively arranged beneath the source region and the drain region, the etch stop layers selectively including at least one of a carbon-doped silicon layer, a non-doped silicon layer, and a boron-doped silicon layer, the etch stop layers forming support structures interposed between the semiconductor substrate and the source and drain regions,
wherein the suspended nanowire channel is formed by etching a sacrificial material beneath the suspended nanowire channel, the etching being selective to the sacrificial material to prevent the removal of the etch stop layers beneath the source region and the drain region.
22. The device of claim 21 , wherein the etch stop layers respectively include the carbon-doped silicon layer arranged immediately under the source or the drain regions and serves as a diffusion stop layer.
23. The device of claim 21 , wherein the etch stop layers respectively include the boron-doped silicon layer arranged immediately on a surface of the substrate and serves as an anti-punch-through layer.