IP Library Granted Patent US 9,178,106
Granted Patent B2
US 9,178,106 · App. 14/059,658 · Granted Nov 3, 2015

Nanowire sized opto-electronic structure and method for modifying selected portions of same

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Quick Facts
Patent No.
US 9,178,106
App. No.
14/059,658
Granted
Nov 3, 2015
Kind
B2
Abstract

A method for treating a LED structure with a substance, the LED structure includes an array of nanowires on a planar support. The method includes producing the substance at a source and causing it to move to the array along a line. The angle between the line followed by the substance and the plane of the support is less than 90° when measured from the center of the support. The substance is capable of rendering a portion of the nanowires nonconductive or less conductive compared to before being treated by the substance.

Claims (29)

1. A method for treating a LED structure with a substance, the LED structure comprising an array of nanowires on a planar support, comprising producing the substance at a source and causing it to move to the array along a line, wherein

(i) the angle between the line followed by the substance and the plane of the support is less than 90° when measured from the center of the support; and

(ii) the substance is capable of rendering a portion of the nanowires nonconductive or less conductive compared to before being treated by the substance; and

wherein the nanowires comprise a tip and a sidewall, and the array comprises edge nanowires and central nanowires, and wherein the angle is such that central nanowires are rendered nonconductive at the tip and along a portion but not all of their sidewall.

2. The method of claim 1 wherein at least one of:

(a) the substance is an insulator and renders the portion of the nanowires nonconductive or less conductive by coating the portion; and

(b) the substance reacts with the portion of the nanowire to render the portion nonconductive or less conductive.

3. The method of claim 2 wherein the substance comprises any of SiO 2 , SiCOH, Al 2 O 3 , SiN, TiO 2 , HfO 2 , or combinations or alloys thereof.

4. The method of claim 1 wherein at least one of:

(a) the angle is less than 45°; and

(b) the substance is produced and caused to move to the nanowires by physical vapor deposition (PVD).

5. The method of claim 4 wherein at least one of:

(a) the angle is less than 30°;

(b) the substance is produced and caused to move to the nanowires by PVD and the PVD comprises electron beam deposition; and

(c) the substance is produced and caused to move to the nanowires by PVD and the PVD comprises sputter deposition.

6. The method of claim 1 wherein the method comprises deposition of a dielectric material and wherein the depth of the dielectric material on the tip of the nanowires is between 50 and 200 nm.

7. The method of claim 1 wherein the nanowires comprise a first conductivity type nanowire core and a second conductivity type nanowire shell, and wherein the first conductivity type semiconductor nanowire core is enclosed by the second conductivity type semiconductor shell for forming a pn or pin junction that in operation provides an active region for light generation.

8. The method of claim 7 wherein at least one of:

(a) the first conductivity type comprises n-type, and the second conductivity type comprises p-type;

(b) the support comprises a n-type buffer layer from which the nanowire core is grown during production of the array of nanowires; and

(c) the support comprises a buffer layer and a dielectric masking layer, such that cores protrude from the buffer layer through openings in the masking layer, and the shells are located on the masking layer.

9. The method of claim 8 wherein the support comprises the buffer layer and at least one of:

(a) the buffer layer comprises at least one of gallium nitride or aluminum gallium nitride;

(b) the support further comprises a substrate layer beneath the buffer layer; and

(c) the support further comprises a reflective layer.

10. The method of claim 9 wherein:

(a) the support further comprises the substrate layer beneath the buffer layer and the substrate layer comprises at least one of Al 2 O 3 , ZnO and Si; and

(b) the support further comprises the reflective layer, and the reflective layer comprises Ag.

11. The method of claim 8 wherein the support comprises the buffer layer, and the method further comprising exposing the buffer layer in a first region of the LED structure.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Apr 12, 2021
From: HERCULES CAPITAL, INC.
To: GLO AB
Reel/Frame 057210/0690 →
SECURITY INTEREST Recorded Jan 23, 2019
From: GLO AB
To: HERCULES CAPITAL INC.
Reel/Frame 048110/0063 →
ASSIGNMENT OF IP SECURITY AGREEMENT Recorded Dec 12, 2018
From: GLO AB
To: HERCULES CAPITAL, INC., AS ADMINISTRATIVE AGENT
Reel/Frame 049042/0527 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 29, 2015
From: HERNER, SCOTT BRAD; THOMPSON, DANIEL BRYCE; LEMAY, CYNTHIA
To: GLO AB
Reel/Frame 036681/0882 →