Dynamic design partitioning for scan chain diagnosis
View Patent ↗Aspects of the invention relate to techniques for chain fault diagnosis based on dynamic circuit design partitioning. Fan-out cones for scan cells of one or more faulty scan chains of a circuit design are determined and combined to derive a forward-tracing cone. Fan-in cones for scan cells of the one or more faulty scan chains and for failing observation points of the circuit design are determined and combined to derive a backward-tracing cone. By determining intersection of the forward-tracing cone and the backward-tracing cone, a chain diagnosis sub-circuit for the test failure file is generated. Using the process, a plurality of chain diagnosis sub-circuits may be generated for a plurality of test failure files. Scan chain fault diagnosis may then be performed on the plurality of chain diagnosis sub-circuits with a plurality of computers.
1. One or more non-transitory processor-readable storage devices storing computer-executable instructions for causing one or more processors to perform a method, the method comprising:
combining fan-out cones for scan cells of one or more faulty scan chains of a circuit design to derive a forward-tracing cone;
combining fan-in cones for scan cells of the one or more faulty scan chains and for failing observation points of the circuit design to derive a backward-tracing cone, the failing observation points comprising scan cells of good scan chains and primary outputs that capture failing bits according to a test failure file; and
generating a chain diagnosis sub-circuit for the test failure file by determining an intersection of the forward-tracing cone and the backward-tracing cone.
2. The one or more non-transitory processor-readable storage devices recited in claim 1 , wherein the method further comprises: performing scan chain fault diagnosis on the chain diagnosis sub-circuit.
3. The one or more non-transitory processor-readable storage devices recited in claim 1 , wherein the method further comprises: repeating the combining fan-out cones and the combining fan-in cones for another test failure file to derive another chain diagnosis sub-circuit for the another test failure file; and performing scan chain fault diagnosis on the chain diagnosis sub-circuit and the another chain diagnosis sub-circuit with a first computer and a second computer, respectively.
4. The one or more non-transitory processor-readable storage devices recited in claim 3 , wherein the combining fan-out cones, combining fan-in cones, and generating are executed by a third computer.
5. The one or more non-transitory processor-readable storage devices recited in claim 1 , wherein the one or more faulty scan chains are identified by a chain pattern test.
6. A method, executed by at least one processor of a computer, comprising:
combining fan-out cones for scan cells of one or more faulty scan chains of a circuit design to derive a forward-tracing cone;
combining fan-in cones for scan cells of the one or more faulty scan chains and for failing observation points of the circuit design to derive a backward-tracing cone, the failing observation points comprising scan cells of good scan chains and primary outputs that capture failing bits according to a test failure file; and
generating a chain diagnosis sub-circuit for the test failure file by determining an intersection of the forward-tracing cone and the backward-tracing cone.
7. The method recited in claim 6 , further comprising:
performing scan chain fault diagnosis on the chain diagnosis sub-circuit.
8. The method recited in claim 6 , further comprising:
repeating the combining fan-out cones and the combining fan-in cones for another test failure file to derive another chain diagnosis sub-circuit for the another test failure file; and
performing scan chain fault diagnosis on the chain diagnosis sub-circuit and the another chain diagnosis sub-circuit with a first computer and a second computer, respectively.
9. The method recited in claim 8 , wherein the combining fan-out cones, combining fan-in cones, and generating are executed by a third computer.
10. The method recited in claim 6 , wherein the one or more faulty scan chains are identified by a chain pattern test.
11. A system comprising:
one or more processors, the one or more processors programmed to perform a method, the method comprising:
combining fan-out cones for scan cells of one or more faulty scan chains of a circuit design to derive a forward-tracing cone;
combining fan-in cones for scan cells of the one or more faulty scan chains and for failing observation points of the circuit design to derive a backward-tracing cone, the failing observation points comprising scan cells of good scan chains and primary outputs that capture failing bits according to a test failure file; and
generating a chain diagnosis sub-circuit for the test failure file by determining an intersection of the forward-tracing cone and the backward-tracing cone.
12. The system recited in claim 11 , wherein the method further comprises:
performing scan chain fault diagnosis on the chain diagnosis sub-circuit.
13. The system recited in claim 12 , wherein the method further comprises:
repeating the combining fan-out cones and the combining fan-in cones for another test failure file to derive another chain diagnosis sub-circuit for the another test failure file; and
performing scan chain fault diagnosis on the chain diagnosis sub-circuit and the another chain diagnosis sub-circuit with a first computer and a second computer, respectively.
14. The system recited in claim 13 , wherein the combining fan-out cones, combining fan-in cones, and generating are executed by a third computer.
15. The system recited in claim 11 , wherein the one or more faulty scan chains are identified by a chain pattern test.