Communication via a memory interface
A memory space of a module connected to a memory controller via a memory interface may be used as a command buffer. Commands received by the module via the command buffer are executed by the module. The memory controller may write to the command buffer out-of-order. The memory controller may delay or eliminate writes to the command buffer. Tags associated with commands are used to specify the order commands are executed. A status buffer in the memory space of the module is used to communicate whether commands have been received or executed. Information received via the status buffer can be used as a basis for a determination to re-send commands to the command buffer.
1. A module, comprising:
a memory interface configured to interface with a memory controller, the memory interface including a memory data interface and a memory command/address interface; and,
the module to execute instructions received via the memory data interface from the memory controller, the instructions to be addressed to a memory space of the module that includes an instruction queue, the instruction queue comprising a plurality of column addresses,
wherein the instructions received via the memory data interface include command tag pairs, each command tag pair including a tag value corresponding to an instruction order bit and a command associated with the instruction order bit,
wherein the instruction order bits determine a relative order of the instructions and the execution of instructions are reordered using the instruction order bits.
2. The module of claim 1 , wherein the memory space further includes a status register space, a plurality of status register space entries each corresponding to a respective entry in the instruction queue.
3. The module of claim 2 , wherein each of the status register space entries, when read by the memory controller, include an indicator of a status of the corresponding entry in the instruction queue.
4. The module of claim 3 , wherein the indicator of the status of an entry in the instruction queue, as read by the memory controller, indicates whether the corresponding entry in the instruction queue has been executed by the module.
5. The module of claim 3 , wherein the indicator of the status of an entry in the instruction queue, as read by the memory controller, indicates whether the corresponding entry in the instruction queue has been received by the module.
6. The module of claim 1 , wherein the instruction queue is managed as a circular buffer.
7. A method of operating a module, comprising:
receiving from a memory controller, via a memory command/address interface, a first write transaction addressed to a first location in an instruction queue in a memory space of the module, the instruction queue comprising a plurality of column addresses;
receiving, via a memory data interface, and by the module, first data corresponding to the first write transaction, the first data including a first instruction to be executed by the module and a first reference tag;
receiving from the memory controller, via the memory interface, a second write transaction addressed to a second location in the instruction queue in the memory space of the module;
receiving, via the memory data interface, and by the module, second data corresponding to the second write transaction, the second data including a second instruction to be executed by the module and a second reference tag;
wherein the first reference tag includes first instruction order bits and the second reference tag includes second instruction order bits, the values of the first and second instruction order bits determining a relative order the first instruction and the second instruction are to be executed by the module; and
reordering the execution of the first and second instructions using the first and second instruction order bits.
8. The method of claim 7 , wherein the first reference tag is associated with a first write completion indicator and a second write completion indicator, the first write completion indicator communicating when a first portion of said first data has been received by the module and the second write completion indicator communicating when a second portion of said first data has been received by the module.
9. The method of claim 7 , further comprising:
receiving from the memory controller, via the memory interface, a first read transaction addressed to a first location in status area in the memory space of the module; and,
in response to the first read transaction, sending, via the memory data interface, third data that includes an indicator of a status of the first write transaction.
10. The method of claim 9 , wherein the indicator of the status of the first write transaction includes an indicator of whether the first write transaction has been received by the module.
11. The method of claim 9 , wherein the indicator of the status of the first write transaction includes an indicator of whether the first instruction has been successfully executed by the module.
12. The method of claim 9 , wherein the first reference tag includes first ordering bits and the third data includes second ordering bits that have the same value as the first ordering bits.
13. A module, comprising:
a command/address interface to receive a first plurality of write commands and first plurality of write addresses from a memory controller, the first plurality of write addresses to be in a command port address space of the module; and,
a data interface to receive a first plurality of data transfers respectively corresponding to the first plurality of write commands from the memory controller, the first plurality of data transfers each indicating a respective command to be executed by the module,
wherein the first plurality of data transfers received via the data interface include command tag pairs, each command tag pair including a tag value corresponding to an instruction order bit and a command associated with the instruction order bit,
wherein the instruction order bits determine a relative order of the commands and the execution of the commands are reordered using the instruction order bits.
14. The module of claim 13 , wherein the command/address interface is to receive a first plurality of read commands and first plurality of read addresses from the memory controller, the first plurality of read addresses to be in a status port address space of the module;
and wherein the data interface is to send a second plurality of data transfers respectively corresponding to the first plurality of read commands, the second plurality of data transfers each including status indicators that respectively indicate a status of the first plurality of write commands.
15. The module of claim 14 , wherein the status indicators signal whether a corresponding one of the first plurality of write commands has been received by the module.
16. The module of claim 14 , wherein the status indicators signal whether a corresponding one of the first plurality of write commands has been executed by the module.
17. The module of claim 14 , wherein the second plurality of data transfers each include a plurality of different valued status tags.