Receiving data streams in parallel and providing a first portion of data to a first state machine engine and a second portion to a second state machine
An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine configured to receive a second portion of the data stream from the processor. The apparatus includes a buffer interface configured to enable data transfer between the first and second state machine engines. The buffer interface includes an interface data bus coupled to the first and second state machine engines. The buffer interface is configured to provide data between the first and second state machine engines.
1. An apparatus, comprising:
a data bus comprising a first plurality of data lines and a second plurality of data lines, wherein the first plurality of data lines is configured to provide data in parallel with the second plurality of data lines, and wherein the first plurality of data lines is different than the second plurality of data lines;
a first state machine engine coupled to the first plurality of data lines; and
a second state machine engine coupled to the second plurality of data lines, wherein the first state machine engine is different than the second state machine engine, wherein the first state machine engine is configured to receive a first portion of a data stream from the first plurality of data lines in parallel with the second state machine engine receiving a second portion of the data stream from the second plurality of data lines, and wherein the first portion of the data stream is different than the second portion of the data stream;
wherein the second state machine engine is configured to provide the second portion of the data stream to the first state machine engine, and the first state machine engine is configured to analyze the first portion of the data stream and the second portion of the data stream.
2. The apparatus of claim 1 , wherein each of the first and second state machine engines comprise a respective state machine lattice having a plurality of configurable elements, and each configurable element of the plurality of configurable elements comprises a plurality of cells configured to analyze at least a portion of the data stream and to output a result of the analysis.
3. The apparatus of claim 1 , comprising an address bus coupled to the first state machine engine and to the second state machine engine.
4. The apparatus of claim 3 , wherein the first and second state machine engines are configured to receive signals from the address bus in parallel.
5. The apparatus of claim 1 , comprising a first control line coupled to the first state machine engine and a second control line coupled to the second state machine engine, wherein the first state machine engine is configured to receive a first set of signals from the first control line in parallel with the second state machine engine receiving a second set of signals from the second control line.
6. The apparatus of claim 1 , wherein the data bus comprises a third plurality of data lines, a fourth plurality of data lines, a fifth plurality of data lines, a sixth plurality of data lines, a seventh plurality of data lines, and an eighth plurality of data lines, wherein the first plurality of data lines is configured to provide data in parallel with the second plurality of data lines, the third plurality of data lines, the fourth plurality of data lines, the fifth plurality of data lines, the sixth plurality of data lines, the seventh plurality of data lines, and the eighth plurality of data lines.
7. The apparatus of claim 6 , comprising:
a third state machine engine coupled to the third plurality of data lines;
a fourth state machine engine coupled to the fourth plurality of data lines;
a fifth state machine engine coupled to the fifth plurality of data lines;
a sixth state machine engine coupled to the sixth plurality of data lines;
a seventh state machine engine coupled to the seventh plurality of data lines; and
an eighth state machine engine coupled to the eighth plurality of data lines.
8. The apparatus of claim 7 , wherein the first state machine engine is configured to receive the first portion of the data stream from the first plurality of data lines in parallel with the second state machine engine receiving the second portion of the data stream from the second plurality of data lines, the third state machine engine receiving a third portion of the data stream from the third plurality of data lines, the fourth state machine engine receiving a fourth portion of the data stream from the fourth plurality of data lines, the fifth state machine engine receiving a fifth portion of the data stream from the fifth plurality of data lines, the sixth state machine engine receiving a sixth portion of the data stream from the sixth plurality of data lines, the seventh state machine engine receiving a seventh portion of the data stream from the seventh plurality of data lines, and the eighth state machine engine receiving an eighth portion of the data stream from the eight plurality of data lines.
9. The apparatus of claim 8 , wherein the third state machine engine is configured to provide the third portion of the data stream to the first state machine engine, the fourth state machine engine is configured to provide the fourth portion of the data stream to the first state machine engine, the fifth state machine engine is configured to provide the fifth portion of the data stream to the first state machine engine, the sixth state machine engine is configured to provide the sixth portion of the data stream to the first state machine engine, the seventh state machine engine is configured to provide the seventh portion of the data stream to the first state machine engine, the eighth state machine engine is configured to provide the eighth portion of the data stream to the first state machine engine, and the first state machine engine is configured to analyze the third portion of the data stream, the fourth portion of the data stream, the fifth portion of the data stream, the sixth portion of the data stream, the seventh portion of the data stream, and the eighth portion of the data stream.
10. The apparatus of claim 1 , wherein the first state machine engine comprises a first buffer configured to store the first portion of the data stream, and the second state machine engine comprises a second buffer configured to store the second portion of the data stream.
11. The apparatus of claim 10 , wherein the first state machine engine comprises a third buffer configured to store the first portion of the data stream and the second portion of the data stream.
12. The apparatus of claim 1 , comprising a buffer interface configured to receive the second portion of the data stream from the second state machine engine and to provide the second portion of the data stream to the first state machine engine.
13. The apparatus of claim 12 , wherein the buffer interface is configured to provide instruction to at least one of the first state machine engine, and the second state machine engine.
14. The apparatus of claim 12 , wherein the first state machine engine comprises a first buffer configured to latch a first set of data provided to the buffer interface and the second state machine engine comprise a second buffer configured to latch a second set of data provided to the buffer interface.
15. The apparatus of claim 14 , wherein the first buffer is configured to latch the first set of data at a first predetermined interval, and the second buffer is configured to latch the second set of data at a second predetermined interval.
16. The apparatus of claim 1 , comprising a module.
17. The apparatus of claim 1 , comprising a data analysis system.
18. The apparatus of claim 1 , wherein each of the first and second state machine engines comprises a separate chip.
19. A method for analyzing data, comprising:
receiving, at a first state machine engine, a first portion of a data stream from a first plurality of data lines of a data bus;
receiving, at a second state machine engine, a second portion of the data stream from a second plurality of data lines of the data bus, wherein the first state machine engine is different than the second state machine engine, wherein the first portion of the data stream is different than the second portion of the data stream, wherein the first plurality of data lines is different than the second plurality of data lines, and wherein the second portion of the data stream is received at the second state machine engine in parallel with the first state machine engine receiving the first portion of the data stream; and
providing the second portion of the data stream from the second state machine engine to the first state machine engine.
20. The method of claim 19 , comprising analyzing the first portion of the data stream and the second portion of the data stream using the first state machine engine.
21. The method of claim 19 , comprising receiving an address signal at the first and second state machine engines to select a first memory address of the first state machine engine and a second memory address of the second state machine engine in parallel.
22. The method of claim 21 , wherein the first memory address is equal to the second memory address.
23. The apparatus of claim 1 , wherein, when the first portion of the data stream and the second portion of the data stream include unequal amounts of data, the first portion of the data stream, the second portion of the data stream, or both, are adjusted using data padding until the first portion of the data stream and the second portion of the data stream include equal amounts of data.
24. The apparatus of claim 23 , wherein the data padding is added in between certain data segments of the first portion of the data stream, the second portion of the data stream, or both, such that data starts and/or stops within the data blocks at predetermined intervals.