Multi-stage translation of prefetch requests
View Patent ↗A device for multi-stage translation of prefetch requests includes a prefetch queue for providing queued prefetch requests, each of the queued prefetch requests including N different control entries; N serial-connected translation stages for the translation of N control entries of one of the queued prefetch requests into a translated prefetch request, wherein a translation in a i-th translation stage is dependent on a translation in a (i−1)-th translation stage, iε[1, . . . , N]; and a prefetch issuer which is configured to control an index for each of the N different control entries in the prefetch queue and to issue a prefetch of the indexed control entry of the N different control entries for the highest non-stalled translation stage.
1. A device for multi-stage translation of prefetch requests, the device comprising:
a prefetch queue for providing queued prefetch requests, each of the queued prefetch requests including N different control entries;
N serial-connected translation stages for the translation of N control entries of one of the queued prefetch requests into a translated prefetch request, wherein a translation in a i-th translation stage is dependent on a translation in a (i−1)-th translation stage, iε[1, . . . , N]; and
a prefetch issuer which is configured to control an index for each of the N different control entries in the prefetch queue and to issue a prefetch of the indexed control entry of the N different control entries for the highest non-stalled translation stage.
2. The device of claim 1 , wherein each translation stage of the N serial-connected translation stages has an allocated cache for caching its translations.
3. The device of claim 1 , wherein the N control entries include N disjunct address parts of a data packet.
4. The device of claim 1 , wherein the index of the highest translation stage of the N serial-connected translation stages is coupled to a head of the prefetch queue.
5. The device of claim 1 , wherein the prefetch issuer is configured to control the indices for prefetches for the N−1 lower translation stages of the N serial-connected translation stages.
6. The device of claim 1 , wherein the i-th translation stage is configured to receive the translation from the (i−1)-th translation stage and the control entries associated with the i-th translation stage and the following N−i translation stages, respectively.
7. The device of claim 6 , wherein the i-th translation stage has at least N−i allocated conflict slots.
8. The device of claim 7 , wherein the i-th translation stage is configured to detect a cache miss in its allocated cache and to send a stall indication to the prefetch issuer, signalling a stall for the translation stage the prefetch request was targeted for.
9. The device of claim 1 , wherein the prefetch issuer includes a multiplexer coupled between the prefetch queue and the lowest translation stage of the N serial-connected translation stages and a controller for controlling the multiplexer such that the prefetch of the indexed control entry of the N different control entries for the highest non-stalled translation stage is issued from the prefetch queue to the lowest translation stage.
10. The device of claim 1 , wherein the prefetch issuer includes N−1 counters for managing the indices for prefetches for the N−1 lower translation stages of the N serial-connected translation stages.
11. The device of claim 1 , wherein the prefetch issuer is configured to issue a prefetch of the indexed control entry for the highest non-stalled translation stage with an update of the least recently used position in the highest non-stalled translation stage, if the index of the control entry associated with the highest non-stalled translation stage corresponds to the index of the control entry associated with the translation stage below the highest non-stalled translation stage.
12. The device of claim 1 , wherein the prefetch issuer is configured to issue a prefetch of the indexed control entry for the highest non-stalled translation stage without an update of the least recently used position in the highest non-stalled translation stage, if the index of the control entry associated with the highest non-stalled translation stage is greater than the index of the control entry associated with the translation stage below the highest non-stalled translation stage.
13. An I/O controller for a processing unit, wherein the I/O controller is coupled to the processing unit and to a memory, wherein the I/O controller includes a device of claim 1 .
14. A method for multi-stage translation of prefetch requests, the method comprising:
providing queued prefetch requests by a prefetch queue, wherein each of the queued prefetch requests including N different control entries;
translating N control entries of one of the queued prefetch requests into a translated prefetch request by N serial-connected translation stages, wherein a translation in an i-th translation stage is dependent on a translation in an (i−1)-th translation stage, iε[1, . . . , N];
controlling an index for each of the N different control entries in the prefetch queue, and
issuing a prefetch of the indexed control entry of the N different control entries for the highest non-stalled translation stage.
15. A computer program comprising a program code for executing the method of claim 14 for multi-stage translation of prefetch requests when run on at least one computer.