IP Library › Granted Patent US 10,067,852

Granted Patent B2

US 10,067,852 · App. 14/066,437 · Granted Sep 4, 2018

Switching between traditional and history program trace modes without halting a processor

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Quick Facts

Patent No.: US 10,067,852
App. No.: 14/066,437
Granted: Sep 4, 2018
Kind: B2

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Abstract

In one or more embodiments, one or more systems, method, and/or processes described herein can change/switch from a first trace mode to a second trace mode without halting a system under development and/or under test. For example, a debug/trace unit can switch a trace mode without halting a processing unit of a system under development and/or under test. For instance, a debug/trace unit can switch a trace mode that can occur on a change of flow boundary of program instructions executable by a processing unit, at a branch instruction, if a region of program instructions is entered or exited, and/or if a capacity of a buffer changes. In one or more embodiments, Nexus messages can be utilized, and trace mode switches can include switches to and/or from traditional and history traces modes.

Claims (53)

1. A system, comprising: a processing unit;

a memory coupled to the processing unit that is configured to store program instructions executable by the processing unit; and

a debug/trace unit coupled to the processing unit;

wherein the processing unit executes a first portion of the program instructions utilizing a first trace mode;

wherein the debug/trace unit:

determines that there is a change of flow boundary of the program instructions based on at least one branch instruction;

determines that the first trace mode is to be switched to a second trace mode based on the change of flow boundary of the program instructions and based on a status of a hardware register of the debug/trace unit; and

switches from the first trace mode to the second trace mode without halting the processing unit to prevent a malfunction of a peripheral when the first and second trace modes are switched, wherein the peripheral consumes data from the processing unit; and

wherein the processing unit executes a second portion of the program instructions utilizing the second trace mode.

2. The system of claim 1 , wherein the processing unit includes at least a portion of the debug/trace unit.

3. The system of claim 1 , wherein the debug/trace unit further determines a capacity of a buffer and determines that the second trace mode is to be switched to the first trace mode based on the capacity of the buffer.

4. The system of claim 1 , wherein the debug/trace unit further determines at least one of a region of the program instructions being entered, the region of the program instructions being exited, a watchpoint being reached, and a breakpoint being reached and determines that the second trace mode is to be switched to the first trace mode based on determining the at least one of the region of the program instructions being entered, the region of the program instructions being exited, the watchpoint being reached, and the breakpoint being reached.

5. The system of claim 1 ,

wherein if the first trace mode is a traditional trace mode and when the debug/trace unit switches from the first trace mode to the second trace mode without halting the processing unit, the debug/trace unit switches from the traditional trace mode to a history trace mode without halting the processing, wherein the history trace mode is the second trace mode; and

wherein if the first trace mode is the history trace mode and when the debug/trace unit switches from the first trace mode to the second trace mode without halting the processing unit, the debug/trace unit switches from the history trace mode to the traditional trace mode without halting the processing, wherein the traditional trace mode is the second trace mode.

6. The system of claim 1 , wherein the processing unit executes the second portion of the program instructions after the debug/trace unit switches from the first trace mode to the second trace mode without halting the processing unit.

7. The system of claim 1 , wherein after the debug/trace unit determines that there is the change of flow boundary of the program instructions, the debug/trace unit further determines that there is not a change of flow boundary of the second portion of the program instructions and determines that the second trace mode is to be switched to the first trace mode based on no change of flow boundary of the program instructions.

8. A debug/trace unit configured to be coupled to a processing unit that is configured to execute program instructions, wherein while the processing unit executes the program instructions the debug/trace unit:

determines that there is a change of flow boundary of the program instructions based on at least one branch instruction;

determines that a first trace mode is to be switched to a second trace mode based on the change of flow boundary of the program instructions and based on a status of a hardware register of the debug/trace unit; and

switches from the first trace mode to the second trace mode without halting the processing unit to prevent a consumption of erroneous data by a peripheral when the first and second trace modes are switched, wherein the peripheral consumes data from the processing unit.

9. The debug/trace unit of claim 8 , wherein the processing unit includes at least a portion of the debug/trace unit.

10. The debug/trace unit of claim 8 , wherein the debug/trace unit further determines a capacity of a buffer and determines that the second trace mode is to be switched to the first trace mode based on the capacity of the buffer.

11. The debug/trace unit of claim 8 , wherein the debug/trace unit further determines at least one of: a region of the program instructions being entered and the region of the program instructions being exited and determines that the second trace mode is to be switched to the first trace mode based on the at least one of the region of the program instructions being entered and the region of the program instructions being exited.

12. The debug/trace unit of claim 8 , wherein in response to the debug/trace unit determining at least one of: a watchpoint being reached and a breakpoint being reached, the debug/trace unit determines that the first trace mode is to be switched to the second trace mode.

13. The debug/trace unit of claim 8 ,

wherein when the debug/trace unit switches from the first trace mode to the second trace mode without halting the processing unit, the processing unit executes a first portion of the program instructions;

wherein after the debug/trace unit switches from the first trace mode to the second trace mode without halting the processing unit, the processing unit executes a second portion of the program instructions; and

wherein the debug/trace unit further determines that there is not a change of flow boundary of the second portion of the program instructions and determines that the second trace mode is to be switched to the first trace mode based on no change of flow boundary of the program instructions.

14. The debug/trace unit of claim 8 ,

15. A method, comprising:

executing first instructions executable by a processing unit;

providing a trace message associated with a first trace mode;

determining that there is a change of flow boundary of the first instructions based on at least one branch instruction;

determining that the first trace mode is to be switched to a second trace mode based on the change of flow boundary of the first instructions and based on a status of a hardware register of a debug/trace unit;

switching from the first trace mode to the second trace mode without halting the processing unit;

preventing a malfunction of a peripheral when the first and second trace modes are switched, wherein the peripheral consumes data from the processing unit; and

executing second instructions executable by the processing unit.

16. The method of claim 15 , further comprising:

determining a capacity of a buffer and determining that the second trace mode is to be switched to the first trace mode.

17. The method of claim 15 , further comprising:

determining at least one of: a region of the first instructions being entered, the region of the first instructions being exited, a watchpoint being reached, and a breakpoint being reached and determining that the second trace mode is to be switched to the first trace mode based on determining the at least one of the region of the first instructions being entered, the region of the first instructions being exited, the watchpoint being reached, and the breakpoint being reached.

18. The method of claim 15 ,

wherein if the first trace mode is a traditional trace mode, switching from the first trace mode to the second trace mode without halting the processing unit includes switching from the traditional trace mode to a history trace mode without halting the processing, wherein the history trace mode is the second trace mode; and

wherein if the first trace mode is the history trace mode, switching from the first trace mode to the second trace mode without halting the processing unit includes switching from the history trace mode to the traditional trace mode without halting the processing, wherein the traditional trace mode is the second trace mode.

19. The method of claim 15 , further comprising:

determining that there is not a change of flow boundary of the second instructions; and

switching from the second trace mode to the first trace mode without halting the processing unit.

20. The method of claim 15 , further comprising:

determining a capacity of a buffer; and

determining that the second trace mode is to be switched to the first trace mode based on the capacity of the buffer.

Assignments (9)

RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019

From: MORGAN STANLEY SENIOR FUNDING, INC.

To: NXP B.V.

Reel/Frame 050744/0097 →

CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040626 FRAME: 0683. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME EFFECTIVE NOVEMBER 7, 2016. Recorded Jan 12, 2017

From: NXP SEMICONDUCTORS USA, INC. (MERGED INTO); FREESCALE SEMICONDUCTOR, INC. (UNDER)

To: NXP USA, INC.

Reel/Frame 041414/0883 →

CHANGE OF NAME Recorded Nov 16, 2016

From: FREESCALE SEMICONDUCTOR INC.

To: NXP USA, INC.

Reel/Frame 040626/0683 →

SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016

From: FREESCALE SEMICONDUCTOR, INC.

To: MORGAN STANLEY SENIOR FUNDING, INC.

Reel/Frame 039138/0001 →

PATENT RELEASE Recorded Dec 21, 2015