Accumulating LDPC (low density parity check) decoder
Accumulating LDPC (Low Density Parity Check) decoder. The accumulating decoding architecture described herein is applicable to LDPC codes operating on a parity check matrix, H, consisting of CSI (Cyclic Shifted Identity) sub-matrices (or matrix sub-blocks) or permuted identity sub-matrices (or matrix sub-blocks). In such a structure, the entire LDPC matrix is broken into square sub-matrices such that each sub-matrix consists of either a CSI sub-matrix or a permuted identity sub-matrix, or a null matrix. The iterative decoding process operates by updating of APP (a posteriori probability) or gamma (γ) values and check edge message (λ) values, and this by updating one or more individual rows within a number of sub-matrix rows (or all sub-matrix or sub-block rows) are processed in parallel. The amount of parallelism is specified by the designer and is typically an integer divisor of the sub-matrix (or sub-block) size.
1. A communication device comprising:
an input configured to receive an low density parity check (LDPC) coded signal via a communication channel from another communication device; and
a processor configured to:
update a first plurality of APP (a posteriori probability) values to generate a second plurality of APP values based on a plurality of differences between a first and a second plurality of check edge messages such that no more than one APP value within any column of an LDPC matrix of the LDPC coded signal is updated during a clock cycle; and
generate a plurality of estimates of bits encoded within the LDPC coded signal using the second plurality of APP values.
2. The communication device of claim 1 further comprising:
the processor configured to update the first plurality of APP values to generate the second plurality of APP values based on a predetermined schedule to ensure that the no more than one APP value within any column of the LDPC matrix is updated during the clock cycle.
3. The communication device of claim 2 further comprising:
the processor configured to update an log-likelihood ratio (LLR) value based on the predetermined schedule using the first and the second plurality of check edge messages.
4. The communication device of claim 1 further comprising:
the processor configured to:
update the first plurality of check edge messages to generate the second plurality of check edge messages by processing a first individual row within a first sub-matrix row and a first individual row within a second sub-matrix row of the LDPC matrix during a first LDPC decoding cycle; and
update the second plurality of check edge messages to generate a third plurality of check edge messages by processing a second individual row within the first sub-matrix row and a second individual row within the second sub-matrix row of the LDPC matrix during a second LDPC decoding cycle.
5. The communication device of claim 1 further comprising:
the processor configured to:
process the LDPC coded signal to generate the first plurality of check edge messages; and
update the first plurality of check edge messages to generate the second plurality of check edge messages.
6. The communication device of claim 1 further comprising:
a daisy chain configured to store at least one of the first and the second plurality of check edge messages for use by the processor in a subsequent LDPC decoding iteration.
7. The communication device of claim 1 further comprising:
a hard limiter configured to process the second plurality of APP values to generate the plurality of estimates of bits encoded within the LDPC coded signal.
8. The communication device of claim 1 further comprising:
the input configured to receive the LDPC coded signal within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.
9. A communication device comprising:
an input configured to receive an low density parity check (LDPC) coded signal via a communication channel from another communication device; and
a processor configured to:
update a first plurality of check edge messages to generate a second plurality of check edge messages by processing a first individual row within a first sub-matrix row and a first individual row within a second sub-matrix row of an LDPC matrix of the LDPC coded signal during a first LDPC decoding cycle; and
update the second plurality of check edge messages to generate a third plurality of check edge messages by processing a second individual row within the first sub-matrix row and a second individual row within the second sub-matrix row of the LDPC matrix during a second LDPC decoding cycle;
update a first plurality of APP (a posteriori probability) values to generate a second plurality of APP values based on at least one of the first, second, and third plurality of check edge messages such that no more than one APP value within any column of the LDPC matrix is updated during a clock cycle; and
generate a plurality of estimates of bits encoded within the LDPC coded signal using the second plurality of APP values.
10. The communication device of claim 9 further comprising:
the processor configured to update the first plurality of APP values to generate the second plurality of APP values based on at least one of a first plurality of differences between the first and the second plurality of check edge messages and a second plurality of differences between the second and the third plurality of check edge messages.
11. The communication device of claim 9 further comprising:
the processor configured to update the first plurality of APP values to generate the second plurality of APP values based on a predetermined schedule to ensure that the no more than one APP value within any column of the LDPC matrix is updated during the clock cycle.
12. The communication device of claim 9 further comprising:
a daisy chain configured to store at least one of the first, the second, and the third plurality of check edge messages for use by the processor in a subsequent LDPC decoding iteration; and
a hard limiter configured to process the second plurality of APP values to generate the plurality of estimates of bits encoded within the LDPC coded signal.
13. The communication device of claim 9 further comprising:
the input configured to receive the LDPC coded signal within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.
14. A method for execution by a communication device, the method comprising:
via an input of the communication device, receiving an low density parity check (LDPC) coded signal via a communication channel from another communication device;
updating a first plurality of APP (a posteriori probability) values to generate a second plurality of APP values based on a plurality of differences between a first and a second plurality of check edge messages such that no more than one APP value within any column of an LDPC matrix of the LDPC coded signal is updated during a clock cycle; and
generating a plurality of estimates of bits encoded within the LDPC coded signal using the second plurality of APP values.
15. The method of claim 14 further comprising:
updating the first plurality of APP values to generate the second plurality of APP values based on a predetermined schedule to ensure that the no more than one APP value within any column of the LDPC matrix is updated during the clock cycle.
16. The method of claim 15 further comprising:
updating an log-likelihood ratio (LLR) value based on the predetermined schedule using the first and the second plurality of check edge messages.
17. The method of claim 14 further comprising:
updating the first plurality of check edge messages to generate the second plurality of check edge messages by processing a first individual row within a first sub-matrix row and a first individual row within a second sub-matrix row of the LDPC matrix during a first LDPC decoding cycle; and
updating the second plurality of check edge messages to generate a third plurality of check edge messages by processing a second individual row within the first sub-matrix row and a second individual row within the second sub-matrix row of the LDPC matrix during a second LDPC decoding cycle.
18. The method of claim 14 further comprising:
processing the LDPC coded signal to generate the first plurality of check edge messages; and
updating the first plurality of check edge messages to generate the second plurality of check edge messages.
19. The method of claim 14 further comprising:
storing at least one of the first and the second plurality of check edge messages in a daisy chain for use in a subsequent LDPC decoding iteration; and
hard limiting the second plurality of APP values to generate the plurality of estimates of bits encoded within the LDPC coded signal.
20. The method of claim 14 further comprising:
receiving the LDPC coded signal within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.