Winding and method for preparing a winding applied to an inductive device
The present invention relates to a winding and a method for preparing a winding of inductive devices. The winding includes at least a plurality of layers, where each layer includes at least one conductive loop; the conductive loops are electrically connected to form a winding; and the conductive loop or the portion of the conductive loop of at least one layer is not spatially aligned with the conductive loop or the portion of the conductive loop of at least one another layer. The winding may be prepared by adopting a PCB process or semiconductor process, which can effectively consume less of surface area on the integration substrate, have a symmetric trace and reduce the parasitic coupling capacitance while acquiring a high Q-factor value. The windings of the present invention may be used for making an inductor or a transformer.
1. A winding comprising:
a plurality of conductive layers, each of the conductive layers comprising at least one conductive loop, the conductive layers being electrically connected to form a winding,
the conductive loop or a geometric center of the conductive loop of at least one layer is not spatially aligned with another conductive loop or a geometric center of the another conductive loop of at least one other conductive layer;
wherein when a plurality of conductive loops are in a nested configuration within a conductive layer, in two adjacent conductive layers when the geometric centers of the conductive loops are not spatially aligned with each other, a distance between an orthogonal projection of the geometric center of a conductive loop of one layer to an adjacent layer, and the geometric center of one loop of the same adjacent layer is 0.5×(W+S), where W is the width of a single loop, and S is the spacing between two adjacent conductive loops which are in a nested configuration within the same layer.
2. The winding according to claim 1 , wherein, except for the conductive loop that includes a center tap, other conductive loops are each divided into 2N loop sections, each loop section being electrically connected to a another loop section of another layer through a pair of crossover conductive via plugs, so as to form N windings, wherein N is an integer greater than or equal to 1.
3. The winding according to claim 1 , wherein, except for the conductive loop that includes a center tap, other conductive loops are each divided into 2N loop sections, each loop section is electrically connected to a another loop section of another layer through a pair of crossover conductive via plugs, so as to form N windings, wherein N is an integer greater than or equal to 1.
4. The winding according to claim 1 , wherein the width of a pair of crossover conductive via plugs does not exceed the width of a conductive loop.
5. The winding according to claim 2 , wherein the width of a pair of crossover conductive via plugs does not exceed the width of a conductive loop.
6. The winding according to claim 3 , wherein the width of a pair of crossover conductive via plugs does not exceed the width of a conductive loop.
7. The winding according claim 1 , wherein the conductive loops of the same layer are electrically connected through cross bridges, the conductive loops are electrically connected to other loops located in a different layer through a pair of crossover conductive via plugs.
8. The winding according to claim 1 , wherein terminal electrodes of each winding are symmetrically adjacent and located in two adjacent loop sections of the same conductive loop.
9. The winding according to claim 2 , wherein terminal electrodes of each winding are symmetrically adjacent and located in two adjacent loop sections of the same conductive loop.
10. The winding according to claim 3 , wherein terminal electrodes of each winding are symmetrically adjacent and located in two adjacent loop sections of the same conductive loop.
11. The winding according to claim 4 , wherein terminal electrodes of each winding are symmetrically adjacent and located in two adjacent loop sections of the same conductive loop.
12. The winding according to claim 5 , wherein terminal electrodes of each winding are symmetrically adjacent and located in two adjacent loop sections of the same conductive loop.
13. The winding according to claim 6 , wherein terminal electrodes of each winding are symmetrically adjacent and located in two adjacent loop sections of the same conductive loop.
14. The winding according to claim 8 , wherein terminal electrodes of the plurality of windings belong to the same conductive loop.
15. The winding according to claim 9 , wherein terminal electrodes of the plurality of windings belong to the same conductive loop.
16. The winding according to claim 10 , wherein terminal electrodes of the plurality of windings belong to the same conductive loop.
17. The winding according to claim 11 , wherein terminal electrodes of the plurality of windings belong to the same conductive loop.
18. The winding according to claim 12 , wherein terminal electrodes of the plurality of windings belong to the same conductive loop.
19. The winding according to claim 13 , wherein terminal electrodes of the plurality of windings belong to the same conductive loop.
20. The winding according to claim 7 , wherein the width of a pair of crossover conductive via plugs does not exceed the width of a conductive loop.
21. The winding according to claim 1 , wherein the conductive loops are in a shape of regular polygon, oval, circle or simple closed curve.
22. The winding according to claim 1 , wherein the widths of different loop sections in the same conductive loop are not completely uniform along the loop.
23. The preparation method of a winding as in claim 1 , at least comprising:
forming the winding on a substrate, wherein, conductive loops are isolated with one another through a dielectric material.
24. The preparation method of a winding as in claim 23 , wherein the substrate comprises a semiconductor substrate or a PCB board.