Granted Patent B2

US 9,437,604 · App. 14/069,553 · Granted Sep 6, 2016

Inventors: Zhenyu Lu (Boise, ID); Roger W. Lindsay (Boise, ID); Andrew Bicksler (Nampa, ID); Yongjun J Hu (Boise, ID); Haitao Liu (Boise, ID)

Assignee: Micron Technology, Inc.

H01L27/11556H01L29/66825H01L29/7926

Abstract

Claims (43)

1. A method comprising:

forming a metal silicide source layer over and in contact with a substrate;

doping the metal silicide source layer;

forming a capping material on the doped metal silicide source layer;

forming a select gate material on the capping material; and

forming a vertical string of floating gate memory cells on the select gate material and extending vertically from the doped metal silicide source layer after forming the metal silicide source layer over the substrate, the vertical string of memory cells including a pillar of semiconductor channel material formed on and extending vertically from and in contact with the doped metal silicide source layer at an ohmic contact, wherein the pillar of semiconductor channel material is not doped.

2. The method of claim 1 wherein forming the string of memory cells comprises:

forming alternating levels of control gate material and insulator material over the select gate material;

forming an opening through the alternating levels of control gate material and insulator material, the select gate material, and the capping material, the opening comprising recesses formed on sidewalls of the opening in the control gate material;

forming a dielectric material over the recesses and the sidewalls of the opening of the alternating levels of control gate material and insulator material;

forming charge storage structures in the recesses;

forming a tunnel dielectric material over the charge storage structures and the sidewalls of the opening of the select gate material; and

forming the channel material in the opening such that the channel material contacts the doped metal silicide source layer.

3. The method of claim 2 and further comprising forming a nitride hard mask over the alternating levels of control gate material and insulator material.

4. The method of claim 2 wherein the dielectric material comprises an oxide-nitride-oxide (ONO) material.

5. The method of claim 2 wherein the tunnel dielectric material and the insulator material comprise an oxide material.

6. The method of claim 2 wherein the select gate material, the control gate material, the charge storage structures, and the channel material comprise a polysilicon.

7. The method of claim 2 and further comprising forming an etch stop material between the select gate material and the alternating levels of control gate material and insulator material.

8. The method of claim 1 and further comprising forming an oxide between the substrate and the doped metal silicide source layer.

9. The method of claim 1 and further comprising forming a polysilicon material between the substrate and the doped metal silicide source layer.

10. The method of claim 1 wherein the metal silicide source layer is one of: tungsten silicide (WSi x ), tantalum silicide (TaSi x ), molybdenum silicide (MoSi x ), or refractory metal silicides.

11. The method of claim 10 wherein “x” ratio is in a range of 1.0 to 4.0.

12. The method of claim 1 wherein the capping material comprises one of an oxide or a polysilicon material.

13. A method comprising:

forming metal silicide source material onto a substrate;

forming an oxide material over the metal silicide source material;

doping the metal silicide source material;

forming a polysilicon select gate material over the oxide material; and

forming a string of floating gate memory cells over the polysilicon select gate material, the string of floating gate memory cells including undoped semiconductor channel material that extends through the polysilicon select gate material and the oxide material to contact the doped metal silicide source material.

14. The method of claim 13 wherein doping the metal silicide source material comprises doping the metal silicide source material with one of arsenic, boron, phosphorus, or gallium.

15. The method of claim 13 wherein doping the metal silicide source material comprises one of: doping the metal silicide material with arsenic or phosphorus to an n-type conductive material or doping the metal silicide source material with boron or gallium to create a p-type conductive material.

16. A method comprising:

forming metal silicide source material onto a substrate;

forming a capping material over the metal silicide source material;

doping the metal silicide source material;

forming a select gate material over the capping material; and

forming a vertical string of floating gate memory cells over the select gate material, in a plurality of alternating levels of control gate material and insulator material, wherein forming the vertical string of memory cells comprises forming a vertical undoped semiconductor material coupled to the doped metal silicide source material and adjacent to the select gate material, wherein the floating gates of the vertical string of memory cells and the select gate material are insulated from the vertical undoped semiconductor material by a tunnel dielectric material.

17. The method of claim 16 wherein forming the vertical string of memory cells comprises:

forming a recess in each level of control gate material;

lining the recess with a dielectric material; and

filling the lined recess with a floating gate material.

18. The method of claim 16 wherein the insulator material and the tunnel dielectric material comprise an oxide material.

19. The method of claim 16 wherein forming the vertical undoped semiconductor material coupled to the doped metal silicide source material comprises forming an ohmic contact between the vertical undoped semiconductor material and the doped metal silicide source material.

Assignments (8)

Continuity (1)