IP Library Granted Patent US 8,853,846
Granted Patent B2
US 8,853,846 · App. 14/072,047 · Granted Oct 7, 2014

Semiconductor device and a manufacturing method of the same

Inventors: Masaki Shiraishi (Hitachi, JP); Tomoaki Uno (Takasaki, JP); Nobuyoshi Matsuura (Takasaki, JP)
Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 8,853,846
App. No.
14/072,047
Granted
Oct 7, 2014
Kind
B2
Abstract

In a non-insulated DC-DC converter having a circuit in which a power MOS•FET high-side switch and a power MOS•FET low-side switch are connected in series, the power MOS•FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS•FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS•FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Claims (19)

1. A semiconductor device comprising:

a semiconductor chip including a schottky barrier diode and a plurality of power MOSFETs which are formed on a single semiconductor substrate;

the semiconductor substrate having a first long side, a second long side located on the opposite side of the first long side, a first short side and a second short side located on the opposite side of the first short side;

the schottky barrier diode formed in a first region of the semiconductor substrate and including an anode electrode and a cathode electrode; and

the plurality of power MOSFETs formed in a plurality of second regions of the semiconductor substrate and respectively including a gate electrode, a source region and a drain region,

wherein a first metal layer is formed over the semiconductor substrate, is electrically connected to the gate electrodes and surrounds the first region and the second regions in a planar view,

wherein a second metal layer is formed over the first region and the second regions and is electrically connected to the source regions and the anode electrode, and

wherein a length along the first long side of the first region is larger than a length along the first short side of the first region.

2. A semiconductor device according to the claim 1 , further comprising:

a plurality of gate fingers unified with the first metal layer, extending to a direction along the first short side and arranged between each of the second regions.

3. A semiconductor device according to the claim 2 ,

wherein, in the direction along the first short side, the first region is arranged between the second regions.

4. A semiconductor device according to the claim 1 ,

wherein each of the gate electrodes is formed in grooves formed in the semiconductor substrate.

5. A semiconductor device according to the claim 4 ,

wherein a length along the first long side of each of the gate electrodes is larger than a length along the first short side of each of the gate electrodes.

6. A semiconductor device according to the claim 1 ,

wherein each of the gate electrodes includes a poly silicon film, and

wherein the first and second metal layers include an aluminum film, respectively.

Assignments (1)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →
Priority Claims (1)
JP 2004-223664 · Jul 30, 2004 · national
Continuity (5)
Continuation 13588538 · Aug 17, 2012
Continuation 13396073 · Feb 14, 2012
Continuation 12686595 · Jan 13, 2010
Continuation 11192069 · Jul 29, 2005
Related Publication 20140054692A1 · Feb 27, 2014