Openflow match and action pipeline structure
An embodiment of the invention includes a packet processing pipeline. The packet processing pipeline includes match and action stages. Each match and action stage in incurs a match delay when match processing occurs and each match and action stage incurs an action delay when action processing occurs. A transport delay occurs between successive match and action stages when data is transferred from a first match and action stage to a second match and action stage.
1. A packet processing pipeline comprising:
a plurality of match and action stages, wherein each match and action stage in the plurality of match and action stages incurs a match delay when match processing occurs; wherein each match and action stage in the plurality of match and action stages incurs an action delay when action processing occurs; wherein a transport delay occurs between successive match and action stages in the plurality of match and action stages when data is transferred from a first match and action stage to a second match and action stage in the successive match and action stages;
wherein each match and action stage of the plurality of match and action stages comprises:
a first crossbar;
an exact match table coupled to the first crossbar;
a second crossbar;
a ternary match table coupled to the second crossbar;
an action memory coupled to the exact match table and the ternary match table; and
an action processor coupled to the action memory.
2. The packet processing pipeline of claim 1 wherein the successive pair of match and action stages have a first field modified by the first match and action stage wherein the modified first field is used as a match field by the second match and action stage.
3. The packet processing pipeline of claim 1 wherein the successive pair of match and action stages have a second field modified by the first match and action stage wherein the modified second field is used as data input to an action by the second match and action stage.
4. The packet processing pipeline of claim 1 where the successive pair of match and action stages have a table successor dependency between the first match and action stage and the second match and action stage.
5. The packet processing pipeline of claim 1 wherein a first time delay between the first and the second match and action stages is approximately equal to the sum of the match delay, the action delay and the transport delay when match processing occurs between the first and the second match and action.
6. The packet processing pipeline of claim 1 wherein a second time delay between the first and the second match and action stages is approximately equal to the sum of the action delay and the transport delay when action processing occurs between the first and the second match and action stages and no action processing occurs between the first and the second match and action stages.
7. The packet processing pipeline of claim 4 wherein a third time delay between the first and the second match and action stages is approximately equal to the transport delay when the table successor dependency occurs between the first and the second match and action stages, no action processing occurs between the first and the second match and action stages and no match processing occurs between the first and the second match and action stages.
8. The packet processing pipeline of claim 1 wherein a fourth time delay between the first and the second match and action stages is approximately equal to the transport delay when no table successor dependency occurs between the first and the second match and action stages, no action processing occurs between the first and the second match and action stages and no match processing occurs between the first and the second match and action stages.