Semiconductor device
View Patent ↗According to one embodiment, the pair of semiconductor regions are provided respectively on a pair of side walls of the second semiconductor layer having the fin configuration to form tunnel junctions with the second semiconductor layer. The gate electrode is provided on two sides of the second semiconductor layer at the pair of side walls to oppose the tunnel junctions with the semiconductor regions interposed between the gate electrode and the tunnel junctions. The third semiconductor layer is separated from the second semiconductor layer and the semiconductor regions by the first semiconductor layer to be adjacent to the first semiconductor layer.
1. A semiconductor device, comprising:
a first semiconductor layer;
a second semiconductor layer of a first conductivity type provided in a fin configuration on the first semiconductor layer, an impurity concentration of the second semiconductor layer being higher than an impurity concentration of the first semiconductor layer;
a pair of semiconductor regions of a second conductivity type provided respectively on a pair of side walls of the second semiconductor layer having the fin configuration to form tunnel junctions with the second semiconductor layer;
a gate electrode provided on two sides of the second semiconductor layer at the pair of side walls to oppose the tunnel junctions with the pair of semiconductor regions interposed between the gate electrode and the tunnel junctions;
a gate insulating film provided between the gate electrode and the pair of semiconductor regions; and
a third semiconductor layer of the second conductivity type separated from the second semiconductor layer and the pair of semiconductor regions by the first semiconductor layer to be adjacent to the first semiconductor layer, an impurity concentration of the third semiconductor layer being higher than the impurity concentration of the first semiconductor layer,
wherein the gate electrode crosses the second semiconductor layer in a width direction of the second semiconductor layer, and
wherein the second semiconductor layer extends in a direction intersecting the crossing direction of the gate electrode.
2. The device according to claim 1 , wherein the pair of semiconductor regions are not provided on an upper surface of the second semiconductor layer, and an insulating layer is provided on the upper surface of the second semiconductor layer.
3. The device according to claim 2 , wherein:
upper surfaces of the pair of semiconductor regions are formed at the same height as the upper surface of the second semiconductor layer, and
the insulating layer is provided on the upper surfaces of the pair of semiconductor regions.
4. The device according to claim 1 , wherein a width of the second semiconductor layer having the fin configuration is not more than 20 nm.
5. The device according to claim 1 , wherein:
the first semiconductor layer has the first conductivity type, and
a p-n diode is formed of the second semiconductor layer, the first semiconductor layer, and the third semiconductor layer.
6. The device according to claim 1 , wherein:
the first semiconductor layer has a protrusion,
the second semiconductor layer is provided on the protrusion, and
the pair of semiconductor regions extend from the side walls of the second semiconductor layer to side walls of the protrusion.
7. The device according to claim 1 , wherein the third semiconductor layer is provided in a region not overlapping the gate electrode, the region being on two sides of the second semiconductor layer in the width direction.
8. The device according to claim 7 , wherein the third semiconductor layer is connected to a contact plug in the region.
9. The device according to claim 1 , wherein a width of the second semiconductor layer is narrower than a width of the gate electrode.
10. The device according to claim 1 , wherein the second semiconductor layer and the pair of semiconductor regions have monocrystalline structures.
11. The device according to claim 1 , wherein a ratio of a height of the second semiconductor layer to a width of the second semiconductor layer is greater than 1.
12. The device according to claim 1 , wherein lower ends of the pair of semiconductor regions contact the first semiconductor layer.
13. The device according to claim 1 , wherein the tunnel junctions are formed at only the side walls of the second semiconductor layer and are not formed at an upper surface of the second semiconductor layer and a lower surface of the second semiconductor layer.
14. The device according to claim 1 , wherein the device is normally-off.
15. The device according to claim 1 , wherein a potential is applied to the second semiconductor layer and the third semiconductor layer to apply a reverse bias to the tunnel junctions.