Spacer etching process for integrated circuit design

1. A method of forming a target pattern for an integrated circuit, the method comprising:

forming a first material layer on a substrate;

performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer, the first layout including a first subset of the target pattern;

performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer, the second layout including a second subset of the target pattern and a cut pattern for the first subset;

forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness, wherein the cut pattern corresponds to a first trench of the second plurality whose width is less than twice the thickness of the spacer features;

removing the first material layer;

etching the substrate using the spacer features as an etch mask; and

thereafter removing the spacer features;

wherein the target pattern is formed with the first layout and the second layout.

2. The method of claim 1 , wherein a portion of the first plurality of trenches is merged with a portion of the second plurality of trenches.

3. The method of claim 1 , wherein performing the first patterning process using the first layout includes:

forming a second material layer over the first material layer;

forming a resist layer over the second material layer;

patterning the resist layer using the first layout thereby resulting in a resist pattern; and

transferring the resist pattern to the first material layer;

wherein the second material is different from the first material.

4. The method of claim 3 , wherein:

the first material includes silicon nitride;

the second material layer includes a bottom layer and a middle layer;

the bottom layer includes a bottom anti-reflection coating polymeric material; and

the middle layer includes silicon-containing polymer.

5. The method of claim 3 , wherein transferring the resist pattern to the first material layer includes:

etching the second material layer using the resist pattern as an etch mask to expose the first material layer;

removing the resist layer;

etching the first material layer using the second material layer as an etch mask to expose the substrate; and

thereafter removing the second material layer.

6. The method of claim 1 , wherein performing the second patterning process using the second layout includes:

forming a second material layer over the first material layer;

forming a third material layer over the second material layer;

forming a resist layer over the third material layer;

patterning the resist layer using the second layout, thereby resulting in a resist pattern; and

transferring the resist pattern to the first material layer;

wherein:

the second material is different from the first material; and

the third material is different from the second material.

7. The method of claim 6 , wherein:

the first material includes silicon nitride;

the second material includes a bottom anti-reflection coating polymeric material; and

the third material includes silicon-containing polymer.

8. The method of claim 6 , wherein transferring the resist pattern to the first material layer includes:

etching the third material layer using the resist pattern as an etch mask to expose the second material layer;

removing the resist layer;

etching the second material layer using the patterned third material layer as an etch mask to expose the first material layer;

removing the third material layer;

etching the first material layer using the patterned second material layer as an etch mask to expose the substrate; and

thereafter removing the second material layer through an etching process selectively tuned to remove the second material while the first material remains.

9. The method of claim 1 , wherein forming the spacer features includes:

depositing a spacer material over the first material layer and on the substrate; and

applying an anisotropic etching process to the spacer material.

10. The method of claim 1 , wherein:

the spacer material includes titanium nitride;

the first material includes silicon nitride;

the substrate includes a nitrogen-free anti-reflection coating layer over an extreme low-k dielectric layer; and

the nitrogen-free anti-reflection coating layer includes a material selected from the group consisting of silicon oxide, silicon oxygen carbide, and plasma enhanced chemical vapor deposited silicon oxide.

11. A method of forming a target pattern, the method comprising:

depositing a first material layer on a substrate;

performing a first lithography patterning process using a first layout to form a first plurality of trenches in the first material layer;

performing a second lithography patterning process using a second layout to form a second plurality of trenches in the first material layer;

forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches using a process including deposition and etching, the spacer features having a thickness;

removing the first material layer by an etching process;

etching the substrate using the spacer features as an etch mask; and

thereafter removing the spacer features using one of: an etching process and a polishing process;

wherein:

the target pattern is formed with the first layout and the second layout;

the first layout includes a first subset of the target pattern;

the second layout includes a second subset of the target pattern and a cut pattern for the first subset; and

the cut pattern corresponds to a portion of the second layout wherein a width of the portion of the second layout is less than twice the thickness of the spacer features.

12. The method of claim 11 , wherein a portion of the first plurality of trenches is merged with a portion of the second plurality of trenches.

13. The method of claim 11 , wherein:

the spacer material includes titanium nitride;

the first material includes silicon nitride;

the substrate includes a nitrogen-free anti-reflection coating layer over an inter-layer dielectric layer; and

the nitrogen-free anti-reflection coating layer uses a material selected from the group consisting of silicon oxide, silicon oxygen carbide, and plasma enhanced chemical vapor deposited silicon oxide.

14. The method of claim 13 , further comprising, forming conductive lines over the substrate using a process including a deposition process and a polishing process, wherein:

the etching of the substrate includes etching the inter-layer dielectric layer thereby forming trenches in the inter-layer dielectric layer;

the deposition process includes filling the trenches in the inter-layer dielectric layer with a conductive material; and

the polishing process includes a chemical mechanical polishing process.

15. The method of claim 11 , further comprising forming an anti-reflection coating layer over the substrate prior to depositing the first material layer on the substrate.

16. The method of claim 11 , wherein one of the first plurality of trenches interfaces with one of the second plurality of trenches to form a continuous trench.

17. The method of claim 16 , wherein forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches includes forming the spacer feature in the continuous trench.

18. A method of forming a target pattern for an integrated circuit, the method comprising:

forming a first material layer on a substrate;

performing a first patterning process using a first layout to form a first plurality of trenches in the first material layer;

performing a second patterning process using a second layout to form a second plurality of trenches in the first material layer, wherein a first trench of the second plurality merges with two trenches of the first plurality;

forming spacer features on sidewalls of both the first plurality of trenches and the second plurality of trenches, the spacer features having a thickness, wherein a width of the first trench is less than twice the thickness of the spacer features thereby the spacer features merge inside the first trench;

removing the first material layer; and

etching the substrate using the spacer features as an etch mask;

wherein the target pattern is formed with the first layout and the second layout.

19. The method of claim 18 , wherein a second trench of the second plurality merges with the two trenches of the first plurality and the second trench has a width greater than twice the thickness of the spacer features.

20. The method of claim 18 , wherein a second trench of the second plurality merges with another trench of the first plurality to form a continuous trench.