Active area shaping of III-nitride devices utilizing a source-side field plate and a wider drain-side field plate

1. A III-nitride semiconductor device comprising:

a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas;

a gate well formed in a dielectric body, said dielectric body situated over said III-nitride heterojunction and including first, second, and third dielectric layers providing respective ledges situated within said gate well;

first and second ohmic electrodes extending through said dielectric body to contact said III-nitride heterojunction;

a single gate dielectric layer situated between said III-nitride heterojunction and said dielectric body, said single gate dielectric layer extending from said first ohmic electrode to said second ohmic electrode;

a gate arrangement situated in said gate well and comprising a gate electrode, a source-side field plate, and a drain-side field plate;

said source-side field plate and said drain-side field plate each comprising steps situated within said gate well and a step situated over said dielectric body, said steps situated within said well being defined by said respective ledges of said first, second, and third dielectric layers;

said step of said drain-side field plate situated over said dielectric body being wider than said step of said source-side field plate situated over said dielectric body, and also being wider than said steps of said drain-side field plate situated within said gate well.

2. The III-nitride semiconductor device of claim 1 , wherein at least one of said steps of said drain-side field plate situated within said well is wider than at least one of said steps of said source-side field plate situated within said well.

3. The III-nitride semiconductor device of claim 1 , wherein one of said steps of said drain-side field plate situated within said well is wider than a corresponding one of said steps of said source-side field plate situated within said well.

4. The III-nitride semiconductor device of claim 1 , wherein at least some of said steps of said drain-side field plate situated within said gate well have different widths from one another.

5. The III-nitride semiconductor device of claim 1 , wherein a closest one of said steps to said gate electrode has a smallest width of said steps within said gate well.

6. The III-nitride semiconductor device of claim 1 , wherein said drain-side field plate is situated over said first, second, and third dielectric layers of said dielectric body, at least one of said first, second, and third dielectric layers being of a different thickness than another of said first, second, and third dielectric layers.

7. The III-nitride semiconductor device of claim 1 , wherein said steps are defined by openings in said dielectric body.

8. The III-nitride semiconductor device of claim 1 , wherein said dielectric body comprises at least one silicon nitride layer and at least one silicon oxide layer.

9. The III-nitride semiconductor device of claim 1 , wherein said source-side field plate and said drain-side field plate are integrated with said gate electrode.

10. A III-nitride semiconductor device comprising:

a III-nitride heterojunction including a first III-nitride body situated over a second III-nitride body to form a two-dimensional electron gas;

a gate well formed in a dielectric body, said dielectric body situated over said III-nitride heterojunction and including first, second, and third dielectric layers providing respective ledges situated within said gate well;

first and second ohmic electrodes extending through said dielectric body to contact said III-nitride heterojunction;

a single gate dielectric layer situated between and adjoining said III-nitride heterojunction and said dielectric body, said single gate dielectric layer extending from said first ohmic electrode to said second ohmic electrode;

a gate arrangement situated in said gate well and comprising a gate electrode, a source-side field plate, and a drain-side field plate;

said source-side field plate and said drain-side field plate each comprising steps situated within said gate well and a step situated over said dielectric body, said steps situated within said well being defined by said respective ledges of said first, second, and third dielectric layers, wherein said step of said drain-side field plate situated over said dielectric body is wider than said step of said source-side field plate situated over said dielectric body, and is also wider than said steps of said drain-side field plate situated within said gate well.

11. The III-nitride semiconductor device of claim 10 , wherein a closest of said steps of said drain-side field plate to said gate electrode is wider than at least one of said steps of said source-side field plate.

12. The III-nitride semiconductor device of claim 10 , wherein said drain-side field plate is wider than said source-side field plate.

13. The III-nitride semiconductor device of claim 10 , wherein at least some of said steps of said drain-side field plate situated within said gate well have different widths from one another.

14. The III-nitride semiconductor device of claim 10 , wherein a closest one of said steps to said gate electrode has a smallest width of said steps within said gate well.

15. The III-nitride semiconductor device of claim 10 , wherein at Least one of said steps of said drain-side field plate and at least one of said steps of said source-side field plate are defined by openings in said dielectric body.

16. The III-nitride semiconductor device of claim 10 , wherein said dielectric body comprises at least one silicon nitride layer and at least one silicon oxide layer.