Semiconductor device and method of manufacturing the same

1. A method of manufacturing a semiconductor device comprising:

forming a first insulating film on a semiconductor layer;

forming a first mask of a charge storing material and a second mask of a charge storing material on the first insulating film, the first mask including a first portion, a second portion, and a third portion extending in a first direction from the first portion to the second portion and connecting the first portion and the second portion, the third portion having a width in a second direction perpendicular to the first direction, and the second mask having a width in a third direction that is wider than the width of the third portion in the second direction, the first mask and the second mask being formed of the same material;

forming a first semiconductor region having a protruded shape and a second semiconductor region having a protruded shape on the semiconductor layer by patterning the first insulating film and the semiconductor layer using the first mask and the second mask, the first semiconductor region including a fourth portion, a fifth portion, and a sixth portion connecting the fourth portion and the fifth portion, and the second semiconductor region having a width in the third direction that is wider than a width of the sixth portion in the second direction;

forming an element isolation insulating film between the first semiconductor region and the second semiconductor region;

performing selective etching so that the third portion of the first mask is removed but the second mask is left by using an etching rate difference between the third portion of the first mask and the second mask;

forming and patterning a second insulating film and a gate electrode material film, thereby forming a gate insulating film and a first gate electrode at least on a top surface of the sixth portion in the first semiconductor region, and forming a tunnel insulating film, a charge storage film, a block insulating film, and a second gate electrode on the second semiconductor region; and

implanting an impurity into the first semiconductor region and the second semiconductor region using the first gate electrode and the second gate electrode as masks, thereby forming first source and drain regions in the fourth portion and the fifth portion of the first semiconductor region, and forming second source and drain regions in the second semiconductor region in a fourth direction perpendicular to the third direction.

2. The method according to claim 1 , wherein the width of the third portion in the second direction is narrower than a width of each of the first portion and the second portion in the second direction, and the width of the six portion in the second direction is narrower than a width of each of the fourth portion and the fifth portion in the second direction.

3. The method according to claim 1 , wherein the first mask and the second mask are formed of a material selected from the group consisting of silicon nitride, polycrystalline silicon, amorphous silicon, microcrystalline silicon, and hafnia.

4. The method according to claim 1 , wherein the semiconductor layer is formed of a material selected from the group consisting of a monocrystalline semiconductor, a polycrystalline semiconductor, and an amorphous semiconductor.

5. A method of manufacturing a semiconductor device comprising:

patterning a semiconductor layer to form a first semiconductor region having a protruded shape and a second semiconductor region having a protruded shape in the semiconductor layer, the first semiconductor region including a first portion, a second portion, and a third portion extending in a first direction from the first portion to the second portion and connecting the first portion and the second portion, the third portion having a width in a second direction perpendicular to the first direction, and the second semiconductor region having a width in a third direction that is wider than the width of the third portion in the second direction;

forming a first insulating film at least on top surfaces of the first semiconductor region and the second semiconductor region;

forming an element isolation insulating film between the first semiconductor region and the second semiconductor region;

forming a charge storing material film covering the first semiconductor region, the second semiconductor region, the first insulating film, and the element isolation film;

selectively etching the charge storing material film to remove at least the charge storing material film on the third portion of the first semiconductor region and to leave the charge storing material film on the second semiconductor region by using an etching rate difference between the charge storing material film on the third portion of the first semiconductor region and the charge storing material film on the second semiconductor region;

forming and patterning a second insulating film and a gate electrode material film to form a gate insulating film and a first gate electrode at least on a top surface of the third portion in the first semiconductor region and to form a tunnel insulating film, a charge storage film, a block insulating film, and a second gate electrode on the second semiconductor region; and

implanting an impurity into the first semiconductor region and the second semiconductor region using the first gate electrode and the second gate electrode as masks, thereby forming first source and drain regions in the first portion and the second portion of the first semiconductor region, and forming second source and drain regions in the second semiconductor region in a fourth direction perpendicular to the third direction.

6. The method according to claim 5 , wherein the width of the third portion in the second direction is narrower than a width of each of the first portion and the second portion in the second direction.

7. The method according to claim 5 , wherein the charge storing material film is formed of a material selected from the group consisting of silicon nitride, polycrystalline silicon, amorphous silicon, microcrystalline silicon, and hafnia.

8. The method according to claim 5 , wherein the semiconductor layer is formed of a material selected from the group consisting of a monocrystalline semiconductor, a polycrystalline semiconductor, and an amorphous semiconductor.

9. A method of manufacturing a semiconductor device comprising:

forming a first insulating film on a semiconductor layer;

forming a first mask and a second mask of an insulating material on the first insulating film, the first mask including a first portion, a second portion, and a third portion extending in a first direction from the first portion to the second portion and connecting the first portion and the second portion, the third portion having a width in a second direction perpendicular to the first direction, and the second mask having a width in a third direction that is wider than the width of the third portion in the second direction;

patterning the first insulating film and the semiconductor layer using the first mask and the second mask to form a first semiconductor region having a protruded shape and a second semiconductor region having a protruded shape in the semiconductor layer, the first semiconductor region including a fourth portion, a fifth portion, and a sixth portion connecting the fourth portion and the fifth portion, a width of the second semiconductor region in the third direction being wider than a width of the sixth portion in the second direction;

performing selective etching to remove the first mask and to leave the second mask by using an etching rate difference between the first mask and the second mask;

implanting a first impurity into at least the sixth portion;

removing the second mask;

forming an element isolation insulating film between the first semiconductor region and the second semiconductor region;

forming a gate electrode material film;

patterning the gate electrode material film to form a first gate electrode and a second gate electrode in the first semiconductor region and the second semiconductor region, respectively; and

implanting a second impurity into the first semiconductor region and the second semiconductor region using the first gate electrode and the second gate electrode as masks, thereby forming first source and drain regions in the fourth portion and the fifth portion of the first semiconductor region, and forming second source and drain regions in the second semiconductor region in a fourth direction perpendicular to the third direction.

10. The method according to claim 9 , wherein the width of the third portion in the second direction is narrower than a width of each of the first portion and the second portion in the second direction, and the width of the six portion in the second direction is narrower than a width of each of the fourth portion and the fifth portion in the second direction.

11. The method according to claim 9 , wherein the first impurity contains at least one element selected from P, As, and B.

12. The method according to claim 9 , wherein the first mask and the second mask are formed of silicon nitride.

13. The method according to claim 9 , wherein the semiconductor layer is formed of a material selected from the group consisting of a monocrystalline semiconductor, a polycrystalline semiconductor, and an amorphous semiconductor.