Method and apparatus for error management of an integrated circuit system
An apparatus and method for error management in an integrated circuit system are presented. An error management unit (EMU) apparatus manages critical and non-critical errors that may be masked or non-masked. An EMU includes an EMU state machine, having a BOOT state, a CONFIG state, a FUNCT state, a WARNING state and an ERROR state. The method discloses transitions in the EMU state machine. While in the ERROR state an error reaction may be applied. The objective of the error reaction is to recover errors by software and hardware means. The EMU may further appropriately alert the system while in ERROR state and therefore be used as a safety mechanism permitting to collect error signals issued by fault detector units and can further cause action on faulty units for recovery purposes.
1. An Error Management Unit comprising:
a circuit for collection of any of critical errors and non-critical errors;
an error reaction module, the error reaction module configured to determine the necessary operation of the Error Management Unit responsive to collected any of critical errors and non-critical errors;
a state machine for controlling the Error Management Unit, the state machine configured to operate in:
a first state present when the Error Management Unit power is reset;
a second state present when the Error Management Unit may be configured;
a third state present when no errors are detected as occurring;
a fourth state present when at least an unmasked non-critical error is signaled and timeout of the at least an unmasked non-critical error is enabled; and,
a fifth state present when at least a critical error or at least an unmasked non-critical error is detected and the Error Management Unit applies an error reaction request to the error reaction module; and
a configuration interface for receiving external configuration information for the Error Management Unit with respect to at least a reaction to the any of critical errors and non-critical errors and any combination thereof.
2. The Error Management Unit of claim 1 , wherein the circuit for collection comprises:
an error tracer, wherein the error tracer is configured to trace the critical errors of the any of critical errors and non-critical errors and further configured to trace unmasked non-critical errors of the any of critical errors and non-critical errors.
3. The Error Management Unit of claim 1 , further comprising:
a Multiple Error Manager, the Multiple Error Manager being operative to manage a plurality of errors, the errors being signaled respective of each other.
4. The Error Management Unit of claim 3 , wherein the Multiple Error Manager is operative to manage a plurality of errors of the any of critical errors and non-critical errors with one of: a replacement policy or a no-replacement policy.
5. The Error Management Unit of claim 3 , wherein the Multiple Error Manager generates a critical error signal in response to two non-critical errors of the any of critical errors and non-critical errors, the two non-critical errors being identified as unmasked and hardware recoverable.
6. The Error Management Unit of claim 3 , wherein the Multiple Error Manager generates a critical error signal in response to three non-critical errors of the any of critical errors and non-critical errors, the three non-critical errors being identified as unmasked and hardware recoverable.
7. The Error Management Unit of claim 3 , wherein the Multiple Error Manager generates a critical error signal in response to two non-critical errors of the any of critical errors and non-critical errors, the two non-critical errors being identified as unmasked and not recoverable.
8. The Error Management Unit of claim 3 , wherein the Multiple Error Manager generates a critical error signal in response to a plurality of non-critical error signals of the any of critical errors and non-critical errors, the plurality of non-critical error signals being identified as unmasked.
9. The Error Management Unit of claim 8 , wherein the plurality of non-critical error signals are cleared and only the critical error is signaled.
10. A method for error control by a state machine of an error management unit, the method comprising:
causing the state machine to reach a first state responsive to a power reset of the Error Management Unit;
causing the state machine to reach a second state responsive of a configuration signal for Error Management Unit configuration;
causing the state machine to reach a third state responsive to detection of an occurrence of at least an error;
causing the state machine to reach a fourth state responsive to at least an unmasked non-critical error of the at least an error is signaled and timeout of the at least an unmasked non-critical error is enabled; and
causing the state machine to reach a fifth state responsive to at least a critical error of the at least an error or at least an unmasked non-critical error of the at least an error is detected responsive of the Error Management Unit asserting an error reaction request.
11. The method of claim 10 , further comprising:
managing a plurality of errors respective of the at least an error, the errors being signaled respective of each other.
12. The method of claim 11 , wherein managing a plurality of errors is performed with one of: a replacement policy or a no-replacement policy.
13. The method of claim 11 , further comprising:
generating a critical error signal in response to two non-critical errors, the two non-critical errors being unmasked and hardware recoverable.
14. The method of claim 11 , further comprising:
generating a critical error signal in response to three non-critical errors, the three non-critical errors being unmasked and hardware recoverable.
15. The method of claim 11 , further comprising:
generating a critical error signal in response to two non-critical errors, the two non-critical errors being unmasked and are not recoverable.
16. The method of claim 11 , further comprising:
generating a critical error signal in response to a plurality of non-critical error signals, the plurality of non-critical error signals being unmasked.
17. The method of claim 16 , wherein the plurality of non-critical error signals are cleared and only the critical error is signaled.