Cascoded semiconductor devices
View Patent ↗The invention provides a cascode transistor circuit with a main power transistor and a cascode MOSFET formed as an integrated circuit, packaged to form the cascode transistor circuit. A control and protection circuit is integrated into the integrated circuit together and a storage capacitor provides an energy source to drive the control and protection circuit. A charging circuit is also integrated into the integrated circuit for charging the storage capacitor.
1. A cascode transistor circuit comprising:
a gallium nitride or silicon carbide field effect transistor having its drain connected to a high power line
a silicon MOSFET with its drain connected to the source of the gallium nitride or silicon carbide FET and its source connected to a low power line and formed as a part of an integrated circuit, wherein the gallium nitride or silicon carbide field effect transistor and the integrated circuit are packaged to form the cascode transistor circuit;
a control and protection circuit integrated into the integrated circuit comprising at least one active component;
wherein the at east one active component comprises a comparator for comparing the MOSFET source voltage with the MOSFET drain voltage and a control switch to turn on the MOSFET when the source voltage exceeds the drain voltage;
a storage capacitor for providing an energy source to drive the active components; and
a charging circuit integrated into the integrated circuit for charging the storage capacitor.
2. A circuit as claimed in claim 1 , wherein the capacitor is integrated into the integrated circuit.
3. A circuit as claimed in claim 1 , wherein the integrated circuit comprises at least three terminals; the MOSFET source, a control input and the MOSFET drain.
4. A circuit as claimed in claim 1 , wherein the control and protection circuit provides protection against over current through the MOSFET.
5. A circuit as claimed in claim 1 , wherein the control and protection circuit provides protection against over temperature.
6. A circuit as claimed in claim 1 , wherein the control and protection circuit provides protection in the event of a detected open loop condition indicative of no connected load connected.
7. A circuit as claimed in claim 1 , having an output pin coupled to an output of the control and protection circuit.
8. A circuit as claimed in claim 7 , wherein the voltage on the output pin or the current flowing to the output pin indicates which protection method or methods are activated.
9. A circuit as claimed in claim 1 , wherein the gallium nitride or silicon carbide FET comprises a high electron mobility transistor and/or wherein the silicon MOSFET comprises a trench MOS transistor.
10. A circuit as claimed in claim 1 , wherein the charging circuit comprises a diode circuit.
11. A circuit as claimed in claim 10 , wherein the charging circuit comprises a diode between the MOSFET drain and the capacitor.
12. A circuit as claimed in claim 10 , wherein the charging circuit comprises a diode between a control input to the cascode transistor circuit and the capacitor.
13. A circuit arrangement comprising:
a cascode transistor circuit as claimed in claim 1 ; and
a gate driver circuit having a single gate output line.
14. A device comprising a circuit arrangement as claimed in claim 13 , wherein the device comprises:
a power supply; or
a power factor correction circuit; or
an inverter circuit; or
a switched mode power converter circuit.