Stair step formation using at least two masks
View Patent ↗Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.
1. A memory, comprising:
a vertical string of memory cells;
horizontal conductive lines coupled to the memory cells, the horizontal conductive lines formed from a stack of alternating conductive materials and insulating materials having a stair step structure at only a portion of one edge of the stack; and
a string driver coupled to the conductive lines via vertical conductors coupled to respective stair steps of the stair step structure.
2. The memory of claim 1 , wherein the stack of alternating conductive materials and insulating materials has the stair step structure on only a portion of the only one edge thereof.
3. The memory of claim 1 , wherein the string of memory cells comprises a three dimensional NAND string.
4. The memory of claim 1 , wherein the stack of alternating conductive materials and insulating materials includes a plurality of stack columns of alternating conductive materials and insulating materials at the only one edge of the stack, the plurality of stack columns arranged side-by-side, and wherein a first one of the stack columns has the stair step structure.
5. The memory of claim 4 , wherein a second one of the stack columns is devoid of the stair step structure.
6. The memory of claim 5 , wherein a third one of the stack columns is devoid of the stair step structure, the third one of the stack columns being a same length as the second one of the stack columns.
7. The memory of claim 4 , wherein the first one of the stack columns is of shorter length than the second one of the stack columns.
8. The memory of claim 4 , wherein the plurality of stack columns include two outer stack columns that are devoid of the stair step structure.
9. The memory of claim 4 , wherein the plurality of stack columns are arranged side-by-side with inner stack columns being located between outer stack columns, and wherein the inner stack columns have the stair step structure and the outer stack columns are devoid of the stair step structure.
10. The memory of claim 9 , wherein the inner stack columns are have a same first length, and the outer stack columns have a same second length, the first length being shorter than the second length.
11. A memory, comprising:
a vertical string of memory cells; and
horizontal conductive lines coupled to the memory cells, the horizontal conductive lines formed from a stack of alternating conductive materials and insulating materials having a stair step structure at only a portion of one edge of the stack.
12. The memory of claim 11 , further comprising a string driver coupled to the conductive lines via vertical conductors coupled to respective stair steps of the stair step structure.
13. The memory of claim 11 , wherein the string of memory cells comprises a three dimensional NAND string.
14. The memory of claim 11 , wherein the stack of alternating conductive materials and insulating materials includes a plurality of stack columns of alternating conductive materials and insulating materials, the plurality of stack columns arranged side-by-side with at least one inner stack column being located between two outer stack of columns, and wherein the at least one inner stack of columns comprises the stair step structure.
15. The memory of claim 14 , wherein the at least one inner stack of columns is of shorter length than the two outer stacks of columns.
16. The memory of claim 15 , wherein the at least one inner stack of columns has a first end located in-line with and adjacent to first ends of the two outer stacks of columns, and the at least one inner stack of columns has a second end located not in line with second ends of the two outer stacks of columns, the stair step structure at the second end of the at least one inner stack of columns.
17. A memory, comprising:
a vertical string of memory cells; and
horizontal conductive lines coupled to the memory cells, the horizontal conductive lines arranged in a stack of conductive materials separated by insulating materials with a plurality of stack columns of alternating conductive materials and insulating materials extending from one edge of the stack, some of the plurality of stack columns having a stair step structure at only a portion of the one edge of the stack.
18. The memory of claim 17 , wherein some of the plurality of stack columns do not have a stair step structure.
19. The memory of claim 18 , wherein the plurality of stack columns that do not have a stair step structure extend further from the stack of conductive materials than the some of the plurality of stack columns that have a stair step structure.
20. The memory of claim 18 , wherein the some of the plurality of stack columns that have a stair step structure extend from nearer a center of the one edge of the stack than the some of the plurality of stack columns that do not have a stair step structure.
21. The memory of claim 18 , wherein the some of the plurality of stack columns that have a stair step structure extend from the one edge of the stack between locations along the one edge of the stack at which respective ones of the some of the plurality of stack columns that do not have a stair step structure extend from the one edge of the stack.
22. The memory of claim 18 , wherein the some of the plurality of stack columns that have a stair step structure extend from nearer a center of the one edge of the stack and a respective stack column that does not have a stair step structure extends from the one edge of the stack nearer between the some of the plurality of stack columns that have a stair step structure and an end of the one edge of the stack.
23. The memory of claim 18 , wherein at least two of the plurality of stack columns have a stair step structure and extend from the one edge of the stack between stack columns that do not have a stair step structure that extend from nearer an end of the one edge of the stack.