Integrated circuit device

1. A packaged optoelectronic chip comprising:

a die including at least one of a radiation emitter and a radiation receiver, the die including a first surface, a second opposed surface, edge surfaces extending in a direction away from the first surface, and bond pads exposed at the first surface of the die;

a transparent packaging layer overlying one of the first and second surfaces of the die, the transparent packaging layer having an inner surface facing the die, an opposed outer surface, and a plurality of edges, the plurality of edges defining a step and each of the plurality of edges having surfaces facing an exterior of the chip package, at least some of the plurality of edges extending at least partially between the inner and outer surfaces of the transparent packaging layer, the at least some of the plurality of edges including a first edge surface bounding an exterior perimeter of the inner surface and a second edge surface bounding an exterior perimeter of the outer surface; and

an opaque layer covering a portion of the transparent packaging layer adjacent at least one of the plurality of edges of the transparent packaging layer.

2. The packaged optoelectronic chip as claimed in claim 1 , wherein the opaque layer covers the plurality of edges defining the step that extend along the opposed outer surface and the second edge surface of the packaging layer.

3. The packaged chip as claimed in claim 1 , wherein at least one of the first and second surfaces of the die has a longest dimension and a major surface of the transparent packaging layer has a longest dimension which exceeds the longest dimension of the die.

4. The packaged chip as claimed in claim 3 , wherein the longest dimension of the transparent packaging layer does not exceed the longest dimension of the one of the first and second surfaces of the die by more than 10%.

5. The packaged chip as claimed in claim 3 , wherein the longest dimension of the transparent packaging layer does not exceed the longest dimension of the one of the first and second surfaces of the die by more than 5%.

6. The packaged chip as claimed in claim 1 , wherein the first surface of the die is a front surface, and the at least one of the radiation emitter or a radiation receiver is disposed adjacent the front surface, and the packaged chip further comprises an insulating layer overlying the second surface of the die.

7. The packaged chip as claimed in claim 1 , further comprising:

an insulating layer having insulated outer edge surfaces and being spaced apart from the transparent packaging layer; and

a plurality of contacts extending along the insulated edge surfaces of the insulating layer and exposed at an exterior of the packaged optoelectronic chip, the plurality of contacts electrically connected to the die,

the die positioned between the insulating layer and the transparent packaging layer.

8. The packaged chip as claimed in claim 1 , further comprising contacts electrically connected to the die.

9. The packaged chip as claimed in claim 8 , wherein said contacts are solderable contacts.

10. The packaged chip as claimed in claim 1 wherein said at least one of a radiation emitter or a radiation receiver is an imaging device.

11. The packaged chip as claimed in claim 1 , further comprising an array of microlenses operatively associated with the die.

12. The packaged chip as claimed in claim 11 , wherein said microlenses are incorporated in said transparent packaging layer.

13. The packaged chip as claimed in claim 1 , further comprising an optical grating operatively associated with the die.

14. The packaged chip as claimed in claim 13 , wherein said optical grating is incorporated in said transparent packaging layer.

15. The packaged chip as claimed in claim 1 , further comprising a wavelength-selective filter operatively associated with the die.

16. A packaged optoelectronic chip comprising:

a die including an active front surface, a rear surface, and at least one of a radiation emitter and a radiation receiver;

a transparent packaging layer overlying the active front surface of the die, the transparent packaging layer having an outer surface facing away from the die, and an edge extending away from the outer surface;

an insulating layer having a bottom surface and an opposed top surface facing the rear surface of the die, the insulated layer spaced apart from the transparent packaging layer and having an insulated edge surface extending between the top and bottom surfaces; and

a plurality of contacts extending along the insulated edge surface and exposed at an exterior portion of the packaged optoelectronic chip, the plurality of contacts electrically connected with the die and spaced apart from the transparent packaging layer,

wherein at least a first portion of the outer surface is exposed at another exterior portion of said packaged optoelectronic chip and an opaque layer covers at least a second portion of the outer surface near the edge.

17. The packaged chip as claimed in claim 16 , wherein the die has a face and edges extending away from the face, the transparent packaging layer extends beyond at least one of the edges of the die, and the opaque layer covers at least a portion of the transparent packaging layer between the at least one of the edges of the die and the edge of the transparent packaging layer.

18. The packaged chip as claimed in claim 16 , wherein a face of the die has a longest dimension and a major surface of the transparent packaging layer has a longest dimension which exceeds the longest dimension of the surface of the die by no more than 20%.

19. The packaged optoelectronic chip of claim 7 , wherein the contacts have an outermost edge surface aligned with the inner surface of the transparent packaging layer in a direction perpendicular to a direction the inner surface of the transparent packaging layer extends.

20. The packaged optoelectronic chip of claim 16 , wherein the die is positioned between the insulating layer and the transparent packaging layer, and the insulating layer has insulated edge surfaces, the packaged chip further comprising:

a plurality of contacts extending along the insulated edge surfaces of the insulating layer and electrically connected to the die, wherein the contacts have an outermost edge surface aligned with an inner surface of the transparent packaging layer in a direction perpendicular to a direction the inner surface of the transparent packaging layer extends and wherein the opaque layer further covers at least a portion of the edge of the transparent packaging layer.