Apparatus and method for applying at-speed functional test with lower-speed tester
A device under test has a connection interface, a controller, and a functional block. The connection interface is used to receive a test pattern transmitted at a first clock rate and output a functional test result. The controller is used to sample the test pattern by using a second clock rate and accordingly generate a sampled test pattern, wherein the second clock rate is higher than the first clock rate. The functional block is used to perform a designated function upon the sampled test pattern and accordingly generate the functional test result.
1. A method for testing a device under test, comprising:
generating at least one test pattern;
feeding the at least one test pattern transmitted at a first clock rate into the device under test;
sampling the at least one test pattern by using a second clock rate and accordingly generate at least one sampled test pattern, wherein the second clock rate is higher than the first clock rate;
performing a designated function upon the at least one sampled test pattern and accordingly generating at least one functional test result;
outputting the at least one functional test result;
wherein the sampling step comprises:
sampling the at least one test pattern by using the second clock rate to generate a plurality of duplicated test patterns served as the at least one sampled test pattern.
2. The method of claim 1 , wherein each test pattern transmitted includes a one-clock-cycle non-all-zero bit pattern sandwiched by a preceding one-clock-cycle all-zero bit pattern and a following one-clock-cycle all-zero bit pattern.
3. The method of claim 2 , wherein the step of generating the at least one test pattern comprises:
generating a first test pattern and a second test pattern, wherein the one-clock-cycle non-all-zero bit pattern included in the first test pattern is identical to the one-clock-cycle non-all-zero bit pattern included in the second test pattern, and the one-clock-cycle non-all-zero bit pattern included in the first test pattern and the one-clock-cycle non-all-zero bit pattern included in the second test pattern are not co-located bit patterns.
4. The method of claim 2 , wherein the step of generating the at least one test pattern comprises:
generating a first test pattern and a second test pattern, wherein the one-clock-cycle non-all-zero bit pattern included in the first test pattern is different from the one-clock-cycle non-all-zero bit pattern included in the second test pattern.
5. The method of claim 4 , wherein the one-clock-cycle non-all-zero bit pattern included in the first test pattern and the one-clock-cycle non-all-zero bit pattern included in the second test pattern have different numbers of 1's included therein.
6. The method of claim 1 , wherein the device under test is a flash memory controller chip.
7. The method of claim 1 , wherein the step of performing the designated function comprises:
utilizing an error checking and correction (ECC) circuit to perform the designated function.
8. The method of claim 7 , wherein the designated function is an ECC decoding operation.
9. The method of claim 8 , wherein the ECC circuit is configured to use shared circuitry to perform an ECC encoding operation and the ECC decoding operation.
10. A method for testing a device under test, comprising:
generating at least one test pattern;
feeding the at least one test pattern transmitted at a first clock rate into the device under test;
sampling the at least one test pattern by using a second clock rate and accordingly generate at least one sampled test pattern, wherein the second clock rate is higher than the first clock rate;
performing a designated function upon the at least one sampled test pattern and accordingly generating at least one functional test result;
outputting the at least one functional test result;
wherein the step of generating the at least one test pattern comprises:
generating the at least one test pattern to intentionally introduce error bits; and
the sampling step comprises:
sampling the at least one test pattern by using the second clock rate to generate a plurality of duplicated test patterns served as the at least one sampled test pattern; and
the step of performing the designated function comprises:
utilizing an error checking and correction (ECC) circuit to perform the designated function.