Method for fabricating a semiconductor device by forming and removing a dummy gate structure

1. A method for fabricating a semiconductor device, comprising:

forming an interlayer dielectric on a substrate;

forming a trench surrounded by the interlayer dielectric;

sequentially and conformally depositing a dielectric layer and a work function layer on a surface of the trench;

filling up the trench with a conductive layer;

removing an upper portion of the conductive layer inside the trench;

forming a protection film on a top surface of the interlayer dielectric and a top surface of the conductive layer after the step of removing the upper portion of the conductive layer inside the trench;

removing the dielectric layer exposed from the protection film; and

forming a hard mask in the trench to cover the protection film.

2. The method according to claim 1 , wherein the interlayer dielectric and the dielectric layer are made of oxides.

3. The method according to claim 1 , wherein both the work function layer and the conductive layer are covered by the protection film.

4. The method according to claim 1 , wherein an etching rate of the dielectric layer is 5 times greater than an etching rate of the protection film during the step of removing the dielectric layer exposed from the protection film.

5. The method according to claim 1 , further comprising removing portions of the work function layer in the trench before removing the dielectric layer.

6. The method according to claim 1 , wherein a process for removing the dielectric layer exposed from the protection film is an isotropic etch process.

7. The method according to claim 6 , further comprising removing the protection layer before a step for forming the hard mask.

8. The method according to claim 1 , wherein the protection film and the hard mask are made of nitrides.

9. The method according to claim 1 , wherein the hard mask comprises a rugged surface, the method further comprising:

depositing a cover layer on the hard mask;

etching portions of the cover layer and portions of the hard mask concurrently so as to obtain an etched hard mask;

removing the cover layer; and

planarizing the etched hard mask.

10. The method according to claim 1 , further comprising planarizing the hard mask until a top surface of the hard mask is level with a top surface of the interlayer dielectric.

11. The method according to claim 10 , further comprising blank etching upper portions of the hard mask before planarizing the hard mask.

12. The method according to claim 10 , before planarizing the hard mask, further comprising:

depositing a patterned cover layer to expose portions of the hard mask; and

etching the hard mask exposed from the cover layer.

13. The method according to claim 1 , before forming the trench, further comprising:

forming a dummy gate structure on the substrate;

forming spacers on sidewalls of the dummy gate respectively;

forming the interlayer dielectric to cover the gate structure and the substrate; and

removing upper portions of the interlayer dielectric until the dummy gate structure is exposed; and

removing the dummy gate structure.

14. The method according to claim 13 , wherein each of the spacers has a multi-layered structure.

15. The method according to claim 14 , wherein the spacers protrude from the ILD after removing the dummy gate structure.

16. The method according to claim 13 , wherein the spacers are in direct contact with the hard mask.

17. The method according to claim 13 , wherein upper portions of the spacers are surrounded by the hard mask.

18. The method according to claim 1 , further comprising forming a recess at a top surface of the interlayer dielectric before the step of depositing the dielectric layer and the work function layer.

19. The method according to claim 18 , wherein the protection film covers the dielectric layer in the recess.