IP Library Granted Patent US 8,972,795
Granted Patent B2
US 8,972,795 · App. 14/091,470 · Granted Mar 3, 2015

Processor system optimization

Inventor: Masaomi Teranishi (Kanagawa, JP)
Assignee: Spansion LLC
G06F9/4881G06F11/3423G06F11/3466G06F11/3452G06F2201/88
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,972,795
App. No.
14/091,470
Granted
Mar 3, 2015
Kind
B2
Abstract

In order to enable the optimization of a processor system without relying upon knowhow or manual labor, an apparatus includes: information obtainment unit for reading, from memory, trace information of the processor system and performance information corresponding to the trace information; information analysis unit for analyzing the trace information and the performance information so as to obtain a performance factor such as an idle time, a processing completion time of a task, or the number of interprocessor communications as a result of the analysis; and optimization method output unit for displaying and outputting a method of optimizing the system in response to a result of the analysis.

Claims (51)

1. An apparatus comprising:

a first processor;

a second processor configured to execute a plurality of tasks with the first processor, wherein at least one task of the plurality of tasks waits for a termination of a communication between a current task and the first processor prior to communication with the first processor; and

an information analysis unit configured to analyze trace information associated with the first and second processors to obtain a performance factor, wherein the performance factor comprises a value of a sum of time periods during which each of the plurality of tasks waits prior to communication with the first processor.

2. The apparatus of claim 1 , further comprising:

an information obtainment unit configured to read, from memory, the trace information and performance information associated with the trace information; and

an optimization method output unit configured to output a method of optimizing the communication between the first and second processors based on the performance factor.

3. The apparatus of claim 2 , wherein the optimization method output unit is configured to output a time chart based on the performance factor, a performance graph based on the performance factor, or a combination thereof.

4. The apparatus of claim 2 , wherein the optimization method output unit is configured to read, from the memory, data from an external environment, wherein the method of optimizing the communication between the first and second processors is based on the data.

5. The apparatus of claim 1 , wherein the performance factor further comprises:

an idle time associated with the each of the plurality of tasks,

a maximum value of a ready time associated with a wait state of each of the plurality of tasks,

a maximum processing completion time of each of the plurality of tasks,

a number of communications between the first processor and the second processor associated with the plurality of tasks,

or a combination thereof.

6. The apparatus of claim 1 , wherein the performance factor further comprises a task execution ratio indicative of a ratio of a time in which a task from the plurality of tasks is in an execution state to a time in which the plurality of tasks is in the execution state.

7. The apparatus of claim 1 , wherein the performance factor further comprises an execution ratio indicative of a ratio of an actual process execution time of each of the plurality of tasks to a sum of execution waiting times and actual process execution times associated with the plurality of tasks.

8. The apparatus of claim 1 , wherein the performance factor further comprises a load ratio indicative of a normalization of processing times associated with the plurality of tasks.

9. A method comprising:

executing a plurality of tasks with a first processor and a second processor;

waiting for a termination of a communication between a current task and the first processor prior to communication of at least one task of the plurality of tasks from the second processor to the first processor; and

analyzing trace information associated with the first and second processors to obtain a performance factor, wherein the performance factor comprises a value of a sum of time periods during which each of the plurality of tasks waits prior to communication with the first processor.

10. The method of claim 9 , further comprising:

reading, from memory, the trace information and performance information associated with the trace information; and

outputting a method of optimizing the communication between the first and second processors based on the performance factor.

11. The method of claim 9 , wherein the analyzing further comprises obtaining the performance factor based on:

an idle time associated with the each of the plurality of tasks,

a maximum value of a ready time associated with a wait state of each of the plurality of tasks,

a maximum processing completion time of each of the plurality of tasks,

a number of communications between the first processor and the second processor associated with the plurality of tasks,

or a combination thereof.

12. The method of claim 9 , wherein the analyzing further comprises obtaining the performance factor based on a task execution ratio indicative of a ratio of a time in which a task from the plurality of tasks is in an execution state to a time in which the plurality of tasks is in the execution state.

13. The method of claim 9 , wherein the analyzing further comprises obtaining the performance factor based on a load ratio indicative of a normalization of processing times associated with the plurality of tasks.

14. A system comprising:

a first processor;

a bus;

a second processor configured to execute a plurality of tasks with the first processor, wherein at least one task of the plurality of tasks waits for a termination of a communication between a current task and the first processor, over the bus, prior to communication with the first processor; and

an information analysis unit configured to analyze trace information associated with the first and second processors to obtain a performance factor, wherein the performance factor comprises a value of a sum of time periods during which each of the plurality of tasks waits prior to communication with the first processor.

15. The system of claim 14 , further comprising:

an information obtainment unit configured to read, from memory, the trace information and performance information associated with the trace information; and

an optimization method output unit configured to output a method of optimizing the communication between the first and second processors based on the performance factor.

16. The system of claim 15 , wherein the performance factor further comprises:

an idle time associated with the each of the plurality of tasks,

a maximum value of a ready time associated with a wait state of each of the plurality of tasks,

a maximum processing completion time of each of the plurality of tasks,

a number of communications between the first processor and the second processor associated with the plurality of tasks,

or a combination thereof.

17. The system of claim 15 , wherein the performance factor further comprises a task execution ratio indicative of a ratio of a time in which a task from the plurality of tasks is in an execution state to a time in which the plurality of tasks is in the execution state.

18. The system of claim 15 , wherein the performance factor further comprises an execution ratio indicative of a ratio of an actual process execution time of each of the plurality of tasks to a sum of execution waiting times and actual process execution times associated with the plurality of tasks.

19. The system of claim 15 , wherein the performance factor further comprises a load ratio indicative of a normalization of processing times associated with the plurality of tasks.

20. The system of claim 15 , wherein the first processor, bus, second processor, and information analysis unit are in an embedded system.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2021
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 058346/0597 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2021
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 058340/0045 →
RELEASE OF SECURITY INTEREST Recorded Sep 14, 2021
From: MUFG UNION BANK, N.A.,
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 057501/0144 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 2, 2014
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 033868/0787 →
Continuity (3)
Continuation 12549708 · Aug 28, 2009
Continuation PCTJP2007000274 · Mar 20, 2007
Related Publication 20140089937A1 · Mar 27, 2014