Nonvolatile semiconductor memory device and control method thereof
View Patent ↗A semiconductor memory device of this embodiment comprises: a plurality of memory chips each including a plurality of memory cells; and a controller that controls the plurality of memory chips. The controller transmits to any of the plurality of memory chips a drive instruction command instructing an operation. The drive instruction command is transmitted sequentially to the plurality of memory chips with at least a first time interval. Each of the plurality of memory chips, when the memory chip itself is in a standby state of waiting for an instruction for one operation execution of an operation loop for a certain operation, starts the operation of the operation loop in response to the drive instruction command, while when the memory chip itself is in operation execution of the operation loop, ignores the drive instruction command.
1. A semiconductor memory device, comprising:
a plurality of memory chips each including a plurality of memory cells; and
a controller that controls the plurality of memory chips,
the controller being configured to transmit to any of the plurality of memory chips a drive instruction command instructing an operation, the drive instruction command being transmitted sequentially to the plurality of memory chips with at least a first time interval, and
each of the plurality of memory chips being configured to, when the memory chip itself is in a standby state of waiting for an instruction for one operation execution of an operational loop for a certain operation, starts the operation of the operational loop in response to the drive instruction command, while when the memory chip itself is in operation execution of the operational loop, ignores the drive instruction command.
2. The semiconductor memory device according to claim 1 , wherein
each of the plurality of memory chips outputs an operation state signal indicating whether the respective memory chip itself has finished the certain operation or not.
3. The semiconductor memory device according to claim 2 , wherein
the controller is configured to determine whether the certain operation in each of the plurality of memory chips has finished or not by receiving the operation state signal.
4. The semiconductor memory device according to claim 1 , wherein
the controller is configured to transmit a status read command to each of the plurality of memory chips along with the drive instruction command, the status read command requesting transmission of data related to a state of each of the plurality of memory chips.
5. The semiconductor memory device according to claim 1 , wherein
the certain operation is a series of operations including repetition of operation of a plurality of operational loops, and
a leading operation of each of the plurality of operational loops is a first operation in which a current value is the largest.
6. The semiconductor memory device according to claim 5 , wherein
each of the plurality of memory chips outputs an operation state signal indicating whether the respective memory chip itself has finished the certain operation or not.
7. The semiconductor memory device according to claim 6 , wherein
the controller is configured to determine whether the certain operation in each of the plurality of memory chips has finished or not by receiving the operation state signal.
8. The semiconductor memory device according to claim 5 , wherein
the controller is configured to transmit a status read signal to each of the plurality of memory chips synchronously with the drive instruction command, the status read signal requesting transmission of data related to a state of each of the plurality of memory chips.
9. A control method of a semiconductor memory device, the semiconductor memory device comprising a plurality of memory chips each including a plurality of memory cells, and a controller that controls the plurality of memory chips, the control method comprising:
transmitting from the controller to any of the plurality of memory chips a drive instruction command instructing an operation, and transmitting the drive instruction command sequentially to the plurality of memory chips with at least a first time interval; and
each of the plurality of memory chips, when the memory chip itself is in a standby state of waiting for an instruction for one operation execution of an operational loop for a certain operation, starting the operation of the operational loop in response to the drive instruction command, while when the memory chip itself is executing the operational loop, ignoring the drive instruction command.
10. The control method of a semiconductor memory device according to claim 9 , further comprising:
each of the plurality of memory chips outputting an operation state signal toward the controller, the operation state signal indicating whether the respective memory chip itself has finished the certain operation or not; and
the controller determining whether the operation in each of the plurality of memory chips has finished or not by receiving the operation state signal.
11. The control method of a semiconductor memory device according to claim 9 , further comprising:
transmitting a status read command from the controller to each of the plurality of memory chips along with the drive instruction command, the status read command requesting transmission of data related to a state of each of the plurality of memory chips; and
each of the plurality of memory chips transmitting the operation state signal to the controller in response to the status read command.
12. The control method of a semiconductor memory device according to claim 9 , wherein
the certain operation is a series of operations including repetition of operation of a plurality of operational loops, and
a leading operation of each of the plurality of operation loops is a first operation in which a current value is the largest.