Semiconductor device and method of making
A semiconductor device is provided. The semiconductor device includes a channel region disposed between a source region and a drain region, a gate structure over the channel region, an interlayer dielectric (ILD) layer proximate the gate structure, an ILD stress layer proximate the top portion of gate structure and over the ILD layer. The gate structure includes a first sidewall, a second sidewall and a top portion. A first stress memorization region is also provided. The first stress memorization region is proximate the top portion of the gate structure. A method of making a semiconductor device is also provided.
1. A semiconductor device, comprising:
a channel region disposed between a source region and a drain region;
a gate structure over the channel region;
an interlayer dielectric (ILD) layer proximate the gate structure and not reaching a to surface of the gate structure; and
an ILD stress layer extending in a direction perpendicular to a sidewall of the gate structure and over the ILD layer.
2. The semiconductor device of claim 1 , comprising:
a first stress memorization region proximate a top portion of the gate structure.
3. The semiconductor device of claim 1 , comprising:
a second stress memorization region in the channel region.
4. The semiconductor device of claim 1 , wherein the ILD stress layer comprises:
at least one of Si, Ge, Ar, Xe, N, F, BF 2 or As.
5. The semiconductor device of claim 1 , wherein the ILD layer extends in the direction perpendicular to the sidewall of the gate structure.
6. The semiconductor device of claim 1 , comprising:
a first gate spacer adjacent the sidewall of the gate structure; and
a second gate spacer adjacent a second sidewall of the gate structure.
7. The semiconductor device of claim 1 , comprising:
a contact etch stop layer (CESL) between at least one of the source region or the drain region and the ILD layer.
8. The semiconductor device of claim 1 , wherein the semiconductor device is a multiple gate field effect transistor (MUGFET).
9. A semiconductor device, comprising:
a channel region disposed between a source region and a drain region;
a gate structure over the channel region;
an interlayer dielectric (ILD) layer extending in a direction perpendicular to a sidewall of the gate structure and not reaching a to surface of the gate structure; and
an ILD stress layer extending in the direction perpendicular to the sidewall of the gate structure and over the ILD layer.
10. The semiconductor device of claim 9 , comprising:
a stress memorization region in the channel region.
11. The semiconductor device of claim 9 , wherein the ILD stress layer comprises:
at least one of Si, Ge, Ar, Xe, N, F, BF 2 or As.
12. The semiconductor device of claim 9 , comprising:
a gate spacer in contact with the gate structure and disposed laterally between the ILD stress layer and the gate structure; and
a contact etch stop layer (CESL) in contact with the gate spacer and disposed laterally between the ILD stress layer and the gate structure.
13. A semiconductor device, comprising:
a first source region;
a first drain region;
a first channel region disposed between the first source region and the first drain region;
a gate structure over the first channel region;
an interlayer dielectric (ILD) layer over at least one of the first source region or the first drain region and not reaching a top surface of the gate structure; and
an ILD stress layer over the ILD layer and extending in a direction perpendicular to a sidewall of the gate structure.
14. The semiconductor device of claim 13 , the ILD stress layer applying a compressive strain on the gate structure.
15. The semiconductor device of claim 13 , comprising:
a contact etch stop layer (CESL) disposed laterally between the ILD stress layer and the gate structure.
16. The semiconductor device of claim 13 , comprising:
a gate spacer disposed laterally between the ILD stress layer and the gate structure.
17. The semiconductor device of claim 13 , comprising:
a contact etch stop layer (CESL) in contact with the ILD stress layer; and
a gate spacer in contact with the CESL and the gate structure.
18. The semiconductor device of claim 17 , wherein the CESL is in contact with the ILD layer.
19. The semiconductor device of claim 13 , wherein the ILD layer is in contact with the ILD stress layer.
20. The semiconductor device of claim 13 , comprising:
a second source region;
a second drain region; and
a second channel region disposed between the second source region and the second drain region, wherein the gate structure is over the second channel region.