Error correction in memory

1. An apparatus, comprising:

a memory device; and

a second memory controller communicatively coupled between the memory device and a first memory controller located at a host system and comprising logic to:

receive a read request from the first memory controller for data stored in the memory device;

retrieve the data and an associated error correction codeword from the memory device;

send the data to the first memory controller at the host system prior to applying an error detection and correction routine;

apply the error detection and correction routine to decode the error correction codeword retrieved with the data; and

in response to detecting an error in the error correction codeword, send a location of data associated with the error to the first memory controller.

2. The apparatus of claim 1 , wherein:

the error correction codeword is a Bose-Chaudhuri-Hocquenghem (BCH) error correction code; and

the error detection and correction routine comprises performing a bitwise XOR of the data retrieved from the memory device.

3. The apparatus of claim 1 , wherein the second memory controller further comprises logic to:

send a clear signal to the first memory controller when the error detection and correction routine indicates that there are no errors in the data.

4. The apparatus of claim 1 , wherein the second memory controller is coupled at the memory device and the first memory controller is separately coupled to a central processing unit package.

5. The apparatus of claim 4 , wherein the first memory controller is integrated into the central processing unit package.

6. An electronic device, comprising:

a processor; and

an apparatus, comprising:

a memory device; and

a second memory controller communicatively coupled between the memory device and a first memory controller located at a host system, and comprising logic to:

receive a read request from the first memory controller for data stored in the memory device;

retrieve the data and an associated error correction codeword from the memory device;

send the data to the first memory controller at the host system prior to applying an error detection and correction routine;

apply the error detection and correction routine to decode the error correction codeword retrieved with the data; and

in response to detecting an error in the error correction codeword, send a location of data associated with the error to the first memory controller.

7. The electronic device of claim 6 , wherein:

the error correction codeword is a Bose-Chaudhuri-Hocquenghem (BCH) error correction code; and

the error detection and correction routine comprises performing a bitwise XOR of the data retrieved from the memory device.

8. The electronic device of claim 6 , wherein the second memory controller further comprises logic to:

send a clear signal to the first memory controller when the error detection and correction routine indicates that there are no errors in the data.

9. The electronic device of claim 6 , wherein the first memory controller is coupled to the processor and comprises logic to:

receive data from the second memory controller;

receive a clear signal from the second memory controller; and

return the data to a requestor in response to the clear signal.

10. The electronic device of claim 6 , wherein the first memory controller is coupled to the processor and comprises logic to:

receive data from the second memory controller;

receive the location in the data of the error from the second memory controller; and

flip a bit value at the location in the data of the error.

11. A method, comprising:

receiving, in a second memory controller, a read request from a first memory controller at a host system communicatively coupled to the second memory controller for data stored in a memory device communicatively coupled to the second memory controller;

retrieving, by the second memory controller, the data and an associated error correction codeword from the memory device;

sending, from the second memory controller, the data to the first memory controller at the host system prior to applying an error detection and correction routine;

applying, in the second memory controller, the error detection and correction routine to decode the error correction codeword retrieved with the data; and

in response to detecting an error in the error correction codeword, sending a location of data associated with the error from the second memory controller to the first memory controller.

12. The method of claim 11 , wherein:

the error correction codeword is a Bose-Chaudhuri-Hocquenghem (BCH) error correction code; and

the error detection and correction routine comprises performing a bitwise XOR of the data retrieved from the memory device.

13. The method of claim 11 , further comprising:

sending, as a signal from the second memory controller, a clear signal to the first memory controller when the error detection and correction routine indicates that there are no errors in the data.

14. The method of claim 13 , further comprising:

receiving, in the first memory controller, data from the second memory controller;

receiving, in the first memory controller, the signal as a clear signal from the second memory controller, and in response to the clear signal, returning the data to a requestor.

15. The method of claim 13 , further comprising:

receiving, in the first memory controller, data from the second memory controller;

receiving, in the first memory controller, the location in the data of the error from the second memory controller; and

flipping a bit value at the location in the data of the error.