Cascode circuit
View Patent ↗A cascode circuit arrangement has a low voltage MOSFET and a depletion mode power device mounted on a substrate (for example a ceramic substrate), which can then be placed in a semiconductor package. This enables inductances to be reduced, and can enable a three terminal packages to be used if desired.
1. A cascode transistor circuit comprising:
a first, depletion mode transistor having its drain for connection to a high power line;
a second, silicon MOSFET with its drain connected to the source of the first transistor and its source for connection to a low power line;
a substrate on which the first and second transistors are mounted, which has a conductive track providing the connection between the source of the first transistor and the drain of the second transistor; and
wherein the first, depletion mode, transistor comprises a high electron mobility transistor or a junction gate field effect transistor.
2. A cascode transistor circuit as claimed in claim 1 , formed as a packaged device, with a first connection from the first transistor drain to a first package terminal, a second connection from the second transistor gate to a second package terminal and a third connection from the second transistor source to a third package terminal, wherein one of the package terminals comprises a die attach pad terminal.
3. A circuit as claimed in claim 2 , wherein the second transistor source connects to the die attach pad terminal.
4. A circuit as claimed in claim 2 , comprising a three terminal package.
5. A circuit as claimed in claim 1 , wherein the second transistor is a vertical device.
6. A circuit as claimed in claim 5 , wherein the second transistor drain is at the bottom.
7. A circuit as claimed in claim 1 , wherein the substrate ( 43 ) comprises a ceramic substrate.
8. A circuit as claimed in claim 1 ,
wherein the first transistor comprises solder bumps and is flip bonded onto the substrate.
9. A circuit as claimed in claim 1 , wherein the second transistor comprises connection clips which connect onto the substrate.
10. A circuit as claimed in claim 1 , comprising further components mounted on the substrate.
11. A circuit as claimed in claim 10 , wherein the further components comprise:
a capacitor, RC snubber circuit or diode for limiting the maximum voltage at the drain of the first transistor point; or
a diode for power factor correction.
12. A circuit as claimed in claim 1 , wherein the first, depletion mode, transistor comprises a GaN transistor.
13. A circuit arrangement comprising:
a cascode transistor circuit as claimed in claim 1 ; and
a gate driver circuit having a single gate output line.
14. A device comprising a circuit arrangement as claimed in claim 13 , wherein the device comprises:
a power supply; or
a power factor correction circuit; or
an inverter circuit; or
a switched mode power converter circuit.
15. A cascode transistor circuit comprising:
a first, depletion mode transistor having its drain for connection to a high power line;
a second, silicon MOSFET with its drain connected to the source of the first transistor and its source for connection to a low power line;
a substrate on which the first and second transistors are mounted, which has a conductive track providing the connection between the source of the first transistor and the drain of the second transistor; and
further components mounted on the substrate, wherein the further components include:
a capacitor, RC snubber circuit or diode for limiting the maximum voltage at the drain of the first transistor point; or
a diode for power factor correction.
16. A circuit arrangement comprising:
a cascode transistor circuit including,
a first, depletion mode transistor having its drain for connection to a high power line;
a second, silicon MOSFET with its drain connected to the source of the first transistor and its source for connection to a low power line;
a substrate on which the first and second transistors are mounted, which has a conductive track providing the connection between the source of the first transistor and the drain of the second transistor; and
a gate driver circuit having a single gate output line.
17. A device comprising a circuit arrangement as claimed in claim 16 , wherein the device comprises:
a power supply; or
a power factor correction circuit; or
an inverter circuit; or
a switched mode power converter circuit.